zig

commit 048035ea555864ff994cee872d5be050d53be38f (tree)
parent 92c262aa9361589dbe6176dbbb8c32a172bdc96c
Author: Koakuma <koachan@protonmail.com>
Date:   Sun, 13 Mar 2022 21:00:16 +0700

stage2 sparcv9: Add Format 1 encoder

Diffstat:
M
src/arch/sparcv9/bits.zig
 | 
12
++++++++++++

1 file changed, 12 insertions(+), 0 deletions(-)
diff --git a/src/arch/sparcv9/bits.zig b/src/arch/sparcv9/bits.zig
@@ -1,5 +1,6 @@
 const std = @import("std");
 const DW = std.dwarf;
+const assert = std.debug.assert;
 const testing = std.testing;
 
 /// General purpose registers in the SPARCv9 instruction set
@@ -448,4 +449,15 @@ pub const Instruction = union(enum) {
     pub fn toU32(self: Instruction) u32 {
         return @bitCast(u32, self);
     }
+
+    fn format1(disp: i32) Instruction {
+        // In SPARC, branch target needs to be aligned to 4 bytes.
+        assert(disp % 4 == 0);
+
+        // Discard the last two bits since those are implicitly zero.
+        const udisp = @truncate(u30, @bitCast(u32, disp) >> 2);
+        return Instruction{ .format_1 = .{
+            .disp30 = udisp,
+        } };
+    }
 };