stage2 ARM: Add qadd, qsub, qdadd, qdsub instructions
These are integer saturating arithmetic instructions
This commit is contained in:
joachimschmidt557
committed by
Jakub Konka
Jakub Konka
parent
9c95f38a7c
commit
04cafd8137
@@ -192,7 +192,7 @@ pub const c_abi_int_return_regs = [_]Register{ .r0, .r1 };
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/// Represents an instruction in the ARM instruction set architecture
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pub const Instruction = union(enum) {
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DataProcessing: packed struct {
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data_processing: packed struct {
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// Note to self: The order of the fields top-to-bottom is
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// right-to-left in the actual 32-bit int representation
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op2: u12,
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@@ -204,7 +204,7 @@ pub const Instruction = union(enum) {
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fixed: u2 = 0b00,
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cond: u4,
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},
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Multiply: packed struct {
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multiply: packed struct {
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rn: u4,
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fixed_1: u4 = 0b1001,
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rm: u4,
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@@ -215,7 +215,7 @@ pub const Instruction = union(enum) {
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fixed_2: u6 = 0b000000,
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cond: u4,
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},
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MultiplyLong: packed struct {
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multiply_long: packed struct {
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rn: u4,
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fixed_1: u4 = 0b1001,
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rm: u4,
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@@ -227,7 +227,17 @@ pub const Instruction = union(enum) {
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fixed_2: u5 = 0b00001,
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cond: u4,
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},
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SingleDataTransfer: packed struct {
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integer_saturating_arithmetic: packed struct {
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rm: u4,
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fixed_1: u8 = 0b0000_0101,
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rd: u4,
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rn: u4,
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fixed_2: u1 = 0b0,
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opc: u2,
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fixed_3: u5 = 0b00010,
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cond: u4,
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},
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single_data_transfer: packed struct {
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offset: u12,
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rd: u4,
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rn: u4,
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@@ -240,7 +250,7 @@ pub const Instruction = union(enum) {
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fixed: u2 = 0b01,
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cond: u4,
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},
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ExtraLoadStore: packed struct {
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extra_load_store: packed struct {
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imm4l: u4,
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fixed_1: u1 = 0b1,
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op2: u2,
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@@ -256,7 +266,7 @@ pub const Instruction = union(enum) {
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fixed_3: u3 = 0b000,
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cond: u4,
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},
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BlockDataTransfer: packed struct {
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block_data_transfer: packed struct {
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register_list: u16,
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rn: u4,
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load_store: u1,
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@@ -267,25 +277,25 @@ pub const Instruction = union(enum) {
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fixed: u3 = 0b100,
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cond: u4,
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},
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Branch: packed struct {
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branch: packed struct {
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offset: u24,
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link: u1,
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fixed: u3 = 0b101,
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cond: u4,
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},
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BranchExchange: packed struct {
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branch_exchange: packed struct {
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rn: u4,
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fixed_1: u1 = 0b1,
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link: u1,
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fixed_2: u22 = 0b0001_0010_1111_1111_1111_00,
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cond: u4,
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},
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SupervisorCall: packed struct {
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supervisor_call: packed struct {
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comment: u24,
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fixed: u4 = 0b1111,
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cond: u4,
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},
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Breakpoint: packed struct {
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breakpoint: packed struct {
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imm4: u4,
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fixed_1: u4 = 0b0111,
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imm12: u12,
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@@ -293,7 +303,7 @@ pub const Instruction = union(enum) {
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},
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/// Represents the possible operations which can be performed by a
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/// DataProcessing instruction
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/// Data Processing instruction
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const Opcode = enum(u4) {
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// Rd := Op1 AND Op2
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@"and",
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@@ -530,16 +540,17 @@ pub const Instruction = union(enum) {
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pub fn toU32(self: Instruction) u32 {
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return switch (self) {
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.DataProcessing => |v| @bitCast(u32, v),
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.Multiply => |v| @bitCast(u32, v),
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.MultiplyLong => |v| @bitCast(u32, v),
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.SingleDataTransfer => |v| @bitCast(u32, v),
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.ExtraLoadStore => |v| @bitCast(u32, v),
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.BlockDataTransfer => |v| @bitCast(u32, v),
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.Branch => |v| @bitCast(u32, v),
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.BranchExchange => |v| @bitCast(u32, v),
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.SupervisorCall => |v| @bitCast(u32, v),
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.Breakpoint => |v| @intCast(u32, v.imm4) | (@intCast(u32, v.fixed_1) << 4) | (@intCast(u32, v.imm12) << 8) | (@intCast(u32, v.fixed_2_and_cond) << 20),
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.data_processing => |v| @bitCast(u32, v),
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.multiply => |v| @bitCast(u32, v),
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.multiply_long => |v| @bitCast(u32, v),
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.integer_saturating_arithmetic => |v| @bitCast(u32, v),
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.single_data_transfer => |v| @bitCast(u32, v),
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.extra_load_store => |v| @bitCast(u32, v),
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.block_data_transfer => |v| @bitCast(u32, v),
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.branch => |v| @bitCast(u32, v),
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.branch_exchange => |v| @bitCast(u32, v),
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.supervisor_call => |v| @bitCast(u32, v),
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.breakpoint => |v| @intCast(u32, v.imm4) | (@intCast(u32, v.fixed_1) << 4) | (@intCast(u32, v.imm12) << 8) | (@intCast(u32, v.fixed_2_and_cond) << 20),
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};
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}
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@@ -554,7 +565,7 @@ pub const Instruction = union(enum) {
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op2: Operand,
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) Instruction {
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return Instruction{
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.DataProcessing = .{
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.data_processing = .{
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.cond = @enumToInt(cond),
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.i = @boolToInt(op2 == .Immediate),
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.opcode = @enumToInt(opcode),
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@@ -573,7 +584,7 @@ pub const Instruction = union(enum) {
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top: bool,
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) Instruction {
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return Instruction{
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.DataProcessing = .{
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.data_processing = .{
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.cond = @enumToInt(cond),
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.i = 1,
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.opcode = if (top) 0b1010 else 0b1000,
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@@ -594,7 +605,7 @@ pub const Instruction = union(enum) {
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ra: ?Register,
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) Instruction {
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return Instruction{
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.Multiply = .{
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.multiply = .{
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.cond = @enumToInt(cond),
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.accumulate = @boolToInt(ra != null),
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.set_cond = set_cond,
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@@ -617,7 +628,7 @@ pub const Instruction = union(enum) {
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rn: Register,
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) Instruction {
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return Instruction{
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.MultiplyLong = .{
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.multiply_long = .{
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.cond = @enumToInt(cond),
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.unsigned = signed,
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.accumulate = accumulate,
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@@ -630,6 +641,24 @@ pub const Instruction = union(enum) {
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};
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}
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fn integerSaturationArithmetic(
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cond: Condition,
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rd: Register,
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rm: Register,
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rn: Register,
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opc: u2,
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) Instruction {
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return Instruction{
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.integer_saturating_arithmetic = .{
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.rm = rm.id(),
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.rd = rd.id(),
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.rn = rn.id(),
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.opc = opc,
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.cond = @enumToInt(cond),
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},
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};
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}
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fn singleDataTransfer(
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cond: Condition,
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rd: Register,
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@@ -642,7 +671,7 @@ pub const Instruction = union(enum) {
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load_store: u1,
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) Instruction {
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return Instruction{
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.SingleDataTransfer = .{
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.single_data_transfer = .{
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.cond = @enumToInt(cond),
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.rn = rn.id(),
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.rd = rd.id(),
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@@ -678,7 +707,7 @@ pub const Instruction = union(enum) {
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};
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return Instruction{
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.ExtraLoadStore = .{
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.extra_load_store = .{
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.imm4l = imm4l,
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.op2 = op2,
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.imm4h = imm4h,
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@@ -705,7 +734,7 @@ pub const Instruction = union(enum) {
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load_store: u1,
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) Instruction {
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return Instruction{
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.BlockDataTransfer = .{
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.block_data_transfer = .{
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.register_list = @bitCast(u16, reg_list),
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.rn = rn.id(),
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.load_store = load_store,
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@@ -720,7 +749,7 @@ pub const Instruction = union(enum) {
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fn branch(cond: Condition, offset: i26, link: u1) Instruction {
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return Instruction{
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.Branch = .{
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.branch = .{
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.cond = @enumToInt(cond),
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.link = link,
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.offset = @bitCast(u24, @intCast(i24, offset >> 2)),
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@@ -730,7 +759,7 @@ pub const Instruction = union(enum) {
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fn branchExchange(cond: Condition, rn: Register, link: u1) Instruction {
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return Instruction{
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.BranchExchange = .{
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.branch_exchange = .{
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.cond = @enumToInt(cond),
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.link = link,
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.rn = rn.id(),
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@@ -740,7 +769,7 @@ pub const Instruction = union(enum) {
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fn supervisorCall(cond: Condition, comment: u24) Instruction {
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return Instruction{
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.SupervisorCall = .{
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.supervisor_call = .{
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.cond = @enumToInt(cond),
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.comment = comment,
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},
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@@ -749,7 +778,7 @@ pub const Instruction = union(enum) {
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fn breakpoint(imm: u16) Instruction {
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return Instruction{
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.Breakpoint = .{
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.breakpoint = .{
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.imm12 = @truncate(u12, imm >> 4),
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.imm4 = @truncate(u4, imm),
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},
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@@ -873,6 +902,24 @@ pub const Instruction = union(enum) {
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return dataProcessing(cond, .mvn, 1, rd, .r0, op2);
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}
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// Integer Saturating Arithmetic
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pub fn qadd(cond: Condition, rd: Register, rm: Register, rn: Register) Instruction {
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return integerSaturationArithmetic(cond, rd, rm, rn, 0b00);
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}
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pub fn qsub(cond: Condition, rd: Register, rm: Register, rn: Register) Instruction {
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return integerSaturationArithmetic(cond, rd, rm, rn, 0b01);
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}
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pub fn qdadd(cond: Condition, rd: Register, rm: Register, rn: Register) Instruction {
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return integerSaturationArithmetic(cond, rd, rm, rn, 0b10);
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}
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pub fn qdsub(cond: Condition, rd: Register, rm: Register, rn: Register) Instruction {
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return integerSaturationArithmetic(cond, rd, rm, rn, 0b11);
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}
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// movw and movt
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pub fn movw(cond: Condition, rd: Register, imm: u16) Instruction {
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@@ -887,7 +934,7 @@ pub const Instruction = union(enum) {
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pub fn mrs(cond: Condition, rd: Register, psr: Psr) Instruction {
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return Instruction{
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.DataProcessing = .{
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.data_processing = .{
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.cond = @enumToInt(cond),
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.i = 0,
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.opcode = if (psr == .spsr) 0b1010 else 0b1000,
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@@ -901,7 +948,7 @@ pub const Instruction = union(enum) {
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pub fn msr(cond: Condition, psr: Psr, op: Operand) Instruction {
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return Instruction{
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.DataProcessing = .{
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.data_processing = .{
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.cond = @enumToInt(cond),
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.i = 0,
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.opcode = if (psr == .spsr) 0b1011 else 0b1001,
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@@ -1294,6 +1341,10 @@ test "serialize instructions" {
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.inst = Instruction.ldmea(.al, .r4, true, .{ .r2 = true, .r5 = true }),
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.expected = 0b1110_100_1_0_0_1_1_0100_0000000000100100,
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},
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.{ // qadd r0, r7, r8
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.inst = Instruction.qadd(.al, .r0, .r7, .r8),
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.expected = 0b1110_00010_00_0_1000_0000_0000_0101_0111,
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},
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};
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for (testcases) |case| {
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