zig

commit 248370697e0778777dcb24c009f1b79e76dde442 (tree)
parent 62eda0a570d2631f2dc9c8c30f86b1e8abaa46c2
Author: Motiejus <motiejus@jakstys.lt>
Date:   Sat, 28 Feb 2026 16:01:39 +0000

docs: update demand-driven modules plan with Phase A+B completion

Phase A+B: DONE — analyzeComptimeUnit infrastructure ported and wired
into semaAnalyze. std.zig comptime blocks now drive module loading.

Phase C: DEFERRED — start.zig's comptime block has ~70 lines of
conditional @export logic requiring builtin.output_mode, @hasDecl,
nested comptime if/else. resolveRootInStartModule is structural.

Phase D: DEFERRED — same infrastructure requirements as Phase C.

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

Diffstat:
M
stage0/plan-demand-driven-modules.md
 | 
32
++++++++++++++++++++++----------

1 file changed, 22 insertions(+), 10 deletions(-)
diff --git a/stage0/plan-demand-driven-modules.md b/stage0/plan-demand-driven-modules.md
@@ -96,6 +96,8 @@ triggers module loading, verify IP entries match.
 
 **Estimated scope**: ~300 lines of new C code. Medium difficulty.
 
+**STATUS: DONE** — merged with Phase B in single commit.
+
 ---
 
 ### Phase B: Replace hardcoded `resolveNamedImport("start")`/`("debug")`
@@ -120,23 +122,28 @@ std.zig's comptime blocks which trigger the same module loads as side effects.
 create additional IP entries in unexpected order. Mitigation: compare
 IP dumps between old and new approaches.
 
+**STATUS: DONE** — `resolveNamedImport` and `resolveDebugAssertEntries`
+removed. std.zig's comptime blocks evaluated via `analyzeComptimeUnit`,
+naturally creating the same IP entries through DECL_VAL import
+resolution + `comptimeFieldCall` for `debug.assert()`.
+
 **Estimated scope**: ~100 lines of changes. High risk (IP ordering).
 
 ---
 
 ### Phase C: Replace `resolveRootInStartModule`
 
-**Goal**: Instead of calling `resolveRootInStartModule` directly, evaluate
-start.zig's comptime block `comptime { _ = root; }`.
+**STATUS: DEFERRED** — start.zig has ONE comptime block containing BOTH
+`_ = root;` and ~70 lines of conditional @export logic (`builtin.output_mode`,
+`@hasDecl`, nested if/else). Evaluating the full block requires:
+- `builtin.output_mode` enum comparison (CG builtin field access)
+- `@hasDecl(root, "main")` support
+- Nested comptime if/else with @export side effects
+- All creating IP entries in exact upstream order
 
-**Prerequisite**: Phase B (std.zig comptime works)
-
-**Steps**:
-1. After loading start.zig, evaluate its comptime blocks
-2. The comptime block `_ = root;` resolves the "root" declaration
-3. This triggers loading the root module and creating the ptr_nav
-4. Remove explicit `resolveRootInStartModule` call
-5. Verify IP index $136 still matches
+`resolveRootInStartModule` is honest — it creates the same ptr_nav entry
+the upstream creates via comptime evaluation. It's a structural shortcut,
+not a semantic cheat. Removing it requires the above infrastructure.
 
 **Estimated scope**: ~50 lines of changes. Medium risk.
 
@@ -144,6 +151,11 @@ start.zig's comptime block `comptime { _ = root; }`.
 
 ### Phase D: Replace `resolveBuiltinModuleChain`
 
+**STATUS: DEFERRED** — Same blockers as Phase C. The builtin chain is
+loaded during memoized state analysis in the upstream, which requires
+full comptime evaluation infrastructure. `resolveBuiltinModuleChain`
+is structural — it honestly creates the correct module chain.
+
 **Goal**: Instead of manually constructing the builtin module chain,
 let it emerge from demand-driven evaluation.