commit 2e1b1728505c20ee38d2bd757148e572e4d95f74 (tree)
parent 874b6e39db08f66bb0f702d2177b91535b2a8a02
Author: David Rubin <david@vortan.dev>
Date: Thu, 27 Nov 2025 17:43:15 -0800
codegen: fix x86-64 backend crc32 inline asm
Diffstat:
3 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/lib/std/hash/crc.zig b/lib/std/hash/crc.zig
@@ -14,7 +14,7 @@ test {
_ = @import("crc/test.zig");
}
-pub const Crc32Iscsi = switch (builtin.cpu.hasAll(.x86, &.{ .@"64bit", .crc32 }) and builtin.zig_backend == .stage2_llvm) {
+pub const Crc32Iscsi = switch (builtin.cpu.hasAll(.x86, &.{ .@"64bit", .crc32 })) {
true => @import("crc/Crc32c.zig"),
else => Crc(u32, .{
.polynomial = 0x1edc6f41,
diff --git a/src/codegen/x86_64/CodeGen.zig b/src/codegen/x86_64/CodeGen.zig
@@ -178018,6 +178018,10 @@ fn airAsm(self: *CodeGen, inst: Air.Inst.Index) !void {
fixed_mnem_size: {
const fixed_mnem_size: Memory.Size = switch (mnem_tag) {
.clflush => .byte,
+ .crc32 => {
+ mnem_size.op_has_size.unset(1);
+ break :fixed_mnem_size;
+ },
.fldcw, .fnstcw, .fstcw, .fnstsw, .fstsw => .word,
.fldenv, .fnstenv, .fstenv => .none,
.frstor, .fsave, .fnsave, .fxrstor, .fxrstor64, .fxsave, .fxsave64 => .none,
diff --git a/tools/update_crc_catalog.zig b/tools/update_crc_catalog.zig
@@ -53,7 +53,7 @@ fn @"i like cheese"(arena: std.mem.Allocator, io: Io, args: []const []const u8)
\\ _ = @import("crc/test.zig");
\\}
\\
- \\pub const Crc32Iscsi = switch (builtin.cpu.hasAll(.x86, &.{ .@"64bit", .crc32 }) and builtin.zig_backend == .stage2_llvm) {
+ \\pub const Crc32Iscsi = switch (builtin.cpu.hasAll(.x86, &.{ .@"64bit", .crc32 })) {
\\ true => @import("crc/Crc32c.zig"),
\\ else => Crc(u32, .{
\\ .polynomial = 0x1edc6f41,