zig

commit 3c2a9220edd59c2d7b50aca65e4cd0748cf2306f (tree)
parent 6c7e66613d57aec2f2949c065ea6431ff6c31f88
Author: g-w1 <jacoblevgw@gmail.com>
Date:   Fri,  8 Jan 2021 17:08:45 -0500

stage2: fix orelse at comptime

There was just some untested code that did not work. .isnull -> .isnonnull
and I had to add a .ref resultloc to make types match up.

Diffstat:
M
src/astgen.zig
 | 
4
++--
M
test/stage2/test.zig
 | 
47
+++++++++++++++++++++++++++++++++++++++++++++++

2 files changed, 49 insertions(+), 2 deletions(-)
diff --git a/src/astgen.zig b/src/astgen.zig
@@ -1127,7 +1127,7 @@ fn catchExpr(mod: *Module, scope: *Scope, rl: ResultLoc, node: *ast.Node.Catch) 
 }
 
 fn orelseExpr(mod: *Module, scope: *Scope, rl: ResultLoc, node: *ast.Node.SimpleInfixOp) InnerError!*zir.Inst {
-    return orelseCatchExpr(mod, scope, rl, node.lhs, node.op_token, .isnull, .unwrap_optional_unsafe, node.rhs, null);
+    return orelseCatchExpr(mod, scope, rl, node.lhs, node.op_token, .isnonnull, .unwrap_optional_unsafe, node.rhs, null);
 }
 
 fn orelseCatchExpr(
@@ -1205,7 +1205,7 @@ fn orelseCatchExpr(
 
     _ = try addZIRInst(mod, &then_scope.base, src, zir.Inst.Break, .{
         .block = block,
-        .operand = try expr(mod, then_sub_scope, branch_rl, rhs),
+        .operand = try rlWrap(mod, then_sub_scope, .{ .ref = {} }, try expr(mod, then_sub_scope, branch_rl, rhs)),
     }, .{});
 
     var else_scope: Scope.GenZIR = .{
diff --git a/test/stage2/test.zig b/test/stage2/test.zig
@@ -1462,4 +1462,51 @@ pub fn addCases(ctx: *TestContext) !void {
             "",
         );
     }
+    {
+        var case = ctx.exe("orelse at comptime", linux_x64);
+        case.addCompareOutput(
+            \\export fn _start() noreturn {
+            \\    const i: ?u64 = 0;
+            \\    const orelsed = i orelse 5;
+            \\    assert(orelsed == 0);
+            \\    exit();
+            \\}
+            \\fn assert(b: bool) void {
+            \\    if (!b) unreachable;
+            \\}
+            \\fn exit() noreturn {
+            \\    asm volatile ("syscall"
+            \\        :
+            \\        : [number] "{rax}" (231),
+            \\          [arg1] "{rdi}" (0)
+            \\        : "rcx", "r11", "memory"
+            \\    );
+            \\    unreachable;
+            \\}
+        ,
+            "",
+        );
+        case.addCompareOutput(
+            \\export fn _start() noreturn {
+            \\    const i: ?u64 = null;
+            \\    const orelsed = i orelse 5;
+            \\    assert(orelsed == 5);
+            \\    exit();
+            \\}
+            \\fn assert(b: bool) void {
+            \\    if (!b) unreachable;
+            \\}
+            \\fn exit() noreturn {
+            \\    asm volatile ("syscall"
+            \\        :
+            \\        : [number] "{rax}" (231),
+            \\          [arg1] "{rdi}" (0)
+            \\        : "rcx", "r11", "memory"
+            \\    );
+            \\    unreachable;
+            \\}
+        ,
+            "",
+        );
+    }
 }