zig

commit 4059242f44e28dc2c8f9837c2033060974fd253f (tree)
parent dd10d3fb5219bb5683b90b4141b0f27eb02dd614
Author: Jacob Young <jacobly0@users.noreply.github.com>
Date:   Thu,  2 Apr 2026 01:49:00 -0400

x86_64: use correct alias for register constraints stored in registers

Closes #31722

Diffstat:
M
src/codegen/x86_64/CodeGen.zig
 | 
16
+++++++++++++---

1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/src/codegen/x86_64/CodeGen.zig b/src/codegen/x86_64/CodeGen.zig
@@ -177226,9 +177226,19 @@ fn airAsm(self: *CodeGen, inst: Air.Inst.Index) !void {
                 'x' => abi.RegisterClass.sse,
                 else => unreachable,
             };
-            if (input_mcv.isRegister() and
-                rc.isSet(RegisterManager.indexOfRegIntoTracked(input_mcv.getReg().?).?))
-                break :arg input_mcv;
+            if (input_mcv.isRegister()) {
+                const reg = input_mcv.getReg().?;
+                if (rc.isSet(RegisterManager.indexOfRegIntoTracked(reg).?)) {
+                    const alias = registerAlias(reg, @intCast(ty.abiSize(zcu)));
+                    break :arg switch (input_mcv) {
+                        else => unreachable,
+                        .register => .{ .register = alias },
+                        .register_offset => |reg_off| .{
+                            .register_offset = .{ .reg = alias, .off = reg_off.off },
+                        },
+                    };
+                }
+            }
             const reg = try self.register_manager.allocReg(null, rc);
             try self.genSetReg(reg, ty, input_mcv, .{});
             break :arg .{ .register = registerAlias(reg, @intCast(ty.abiSize(zcu))) };