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Merge pull request #21894 from alexrp/aarch64-big-endian

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Disable some failing tests and add `aarch64_be-linux-(none,gnu,musl)` to CI
This commit is contained in:
Alex Rønne Petersen
2024-11-04 13:54:56 +01:00
committed by GitHub
parent 6b2c8fc688 af71694dd9
commit 4a3611f7d6
10 changed files with 54 additions and 21 deletions
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4
lib/std/debug.zig
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@@ -1335,7 +1335,11 @@ fn dumpSegfaultInfoPosix(sig: i32, code: i32, addr: usize, ctx_ptr: ?*anyopaque)
.x86,
.x86_64,
.arm,
.armeb,
.thumb,
.thumbeb,
.aarch64,
.aarch64_be,
=> {
const ctx: *posix.ucontext_t = @ptrCast(@alignCast(ctx_ptr));
dumpStackTraceFromBase(ctx);

18
lib/std/debug/Dwarf/abi.zig
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@@ -35,8 +35,8 @@ pub fn ipRegNum(arch: Arch) ?u8 {
return switch (arch) {
.x86 => 8,
.x86_64 => 16,
.arm => 15,
.aarch64 => 32,
.arm, .armeb, .thumb, .thumbeb => 15,
.aarch64, .aarch64_be => 32,
else => null,
};
}
@@ -47,8 +47,8 @@ pub fn fpRegNum(arch: Arch, reg_context: RegisterContext) u8 {
// (only in .eh_frame), and that is now the convention for MachO
.x86 => if (reg_context.eh_frame and reg_context.is_macho) 4 else 5,
.x86_64 => 6,
.arm => 11,
.aarch64 => 29,
.arm, .armeb, .thumb, .thumbeb => 11,
.aarch64, .aarch64_be => 29,
else => unreachable,
};
}
@@ -57,8 +57,8 @@ pub fn spRegNum(arch: Arch, reg_context: RegisterContext) u8 {
return switch (arch) {
.x86 => if (reg_context.eh_frame and reg_context.is_macho) 5 else 4,
.x86_64 => 7,
.arm => 13,
.aarch64 => 31,
.arm, .armeb, .thumb, .thumbeb => 13,
.aarch64, .aarch64_be => 31,
else => unreachable,
};
}
@@ -131,7 +131,7 @@ pub fn regBytes(
16 => mem.asBytes(&thread_context_ptr.Rip),
else => error.InvalidRegister,
},
.aarch64 => switch (reg_number) {
.aarch64, .aarch64_be => switch (reg_number) {
0...30 => mem.asBytes(&thread_context_ptr.DUMMYUNIONNAME.X[reg_number]),
31 => mem.asBytes(&thread_context_ptr.Sp),
32 => mem.asBytes(&thread_context_ptr.Pc),
@@ -269,7 +269,7 @@ pub fn regBytes(
},
else => error.UnimplementedOs,
},
.arm => switch (builtin.os.tag) {
.arm, .armeb, .thumb, .thumbeb => switch (builtin.os.tag) {
.linux => switch (reg_number) {
0 => mem.asBytes(&ucontext_ptr.mcontext.arm_r0),
1 => mem.asBytes(&ucontext_ptr.mcontext.arm_r1),
@@ -292,7 +292,7 @@ pub fn regBytes(
},
else => error.UnimplementedOs,
},
.aarch64 => switch (builtin.os.tag) {
.aarch64, .aarch64_be => switch (builtin.os.tag) {
.macos, .ios, .watchos => switch (reg_number) {
0...28 => mem.asBytes(&ucontext_ptr.mcontext.ss.regs[reg_number]),
29 => mem.asBytes(&ucontext_ptr.mcontext.ss.fp),

10
lib/std/debug/SelfInfo.zig
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@@ -1419,7 +1419,7 @@ pub fn unwindFrameMachO(
return unwindFrameMachODwarf(context, ma, eh_frame orelse return error.MissingEhFrame, @intCast(encoding.value.x86_64.dwarf));
},
},
.aarch64 => switch (encoding.mode.arm64) {
.aarch64, .aarch64_be => switch (encoding.mode.arm64) {
.OLD => return error.UnimplementedUnwindEncoding,
.FRAMELESS => blk: {
const sp = (try regValueNative(context.thread_context, spRegNum(reg_context), reg_context)).*;
@@ -1535,7 +1535,7 @@ pub const UnwindContext = struct {
/// Some platforms use pointer authentication - the upper bits of instruction pointers contain a signature.
/// This function clears these signature bits to make the pointer usable.
pub inline fn stripInstructionPtrAuthCode(ptr: usize) usize {
if (native_arch == .aarch64) {
if (native_arch.isAARCH64()) {
// `hint 0x07` maps to `xpaclri` (or `nop` if the hardware doesn't support it)
// The save / restore is because `xpaclri` operates on x30 (LR)
return asm (
@@ -1787,11 +1787,11 @@ pub fn supportsUnwinding(target: std.Target) bool {
.linux, .netbsd, .freebsd, .openbsd, .macos, .ios, .solaris, .illumos => true,
else => false,
},
.arm => switch (target.os.tag) {
.arm, .armeb, .thumb, .thumbeb => switch (target.os.tag) {
.linux => true,
else => false,
},
.aarch64 => switch (target.os.tag) {
.aarch64, .aarch64_be => switch (target.os.tag) {
.linux, .netbsd, .freebsd, .macos, .ios => true,
else => false,
},
@@ -2194,7 +2194,7 @@ pub const VirtualMachine = struct {
/// the .undefined rule by default, but allows ABI authors to override that.
fn getRegDefaultValue(reg_number: u8, context: *UnwindContext, out: []u8) !void {
switch (builtin.cpu.arch) {
.aarch64 => {
.aarch64, .aarch64_be => {
// Callee-saved registers are initialized as if they had the .same_value rule
if (reg_number >= 19 and reg_number <= 28) {
const src = try regBytes(context.thread_context, reg_number, context.reg_context);

1
lib/std/simd.zig
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@@ -462,6 +462,7 @@ pub fn prefixScan(comptime op: std.builtin.ReduceOp, comptime hop: isize, vec: a
test "vector prefix scan" {
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
if (builtin.cpu.arch == .aarch64_be and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest; // https://github.com/ziglang/zig/issues/21893
if (comptime builtin.cpu.arch.isMIPS()) {
return error.SkipZigTest;

3
test/behavior/atomics.zig
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@@ -5,7 +5,8 @@ const expectEqual = std.testing.expectEqual;
const supports_128_bit_atomics = switch (builtin.cpu.arch) {
// TODO: Ideally this could be sync'd with the logic in Sema.
.aarch64, .aarch64_be => true,
.aarch64 => true,
.aarch64_be => false, // Fails due to LLVM issues.
.x86_64 => std.Target.x86.featureSetHas(builtin.cpu.features, .cx16),
else => false,
};

1
test/behavior/bitcast.zig
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@@ -402,6 +402,7 @@ test "bitcast vector to integer and back" {
if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
if (builtin.cpu.arch == .aarch64_be and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest;
const arr: [16]bool = [_]bool{ true, false } ++ [_]bool{true} ** 14;
var x: @Vector(16, bool) = @splat(true);

4
test/behavior/union.zig
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@@ -1820,10 +1820,8 @@ test "reinterpret packed union" {
try comptime S.doTheTest();
if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO
if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest; // https://github.com/ziglang/zig/issues/21050
if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest; // https://github.com/ziglang/zig/issues/21050
if (builtin.cpu.arch.isWasm()) return error.SkipZigTest; // TODO
if (builtin.cpu.arch == .s390x and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest; // TODO
if (builtin.cpu.arch.endian() == .big) return error.SkipZigTest; // https://github.com/ziglang/zig/issues/21050
try S.doTheTest();
}

7
test/behavior/vector.zig
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@@ -1060,6 +1060,7 @@ test "@addWithOverflow" {
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
if (builtin.cpu.arch == .aarch64_be and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest;
const S = struct {
fn doTheTest() !void {
@@ -1108,6 +1109,7 @@ test "@subWithOverflow" {
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
if (builtin.cpu.arch == .aarch64_be and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest;
const S = struct {
fn doTheTest() !void {
@@ -1140,6 +1142,7 @@ test "@mulWithOverflow" {
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
if (builtin.cpu.arch == .aarch64_be and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest;
const S = struct {
fn doTheTest() !void {
@@ -1162,6 +1165,7 @@ test "@shlWithOverflow" {
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
if (builtin.cpu.arch == .aarch64_be and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest;
const S = struct {
fn doTheTest() !void {
@@ -1245,6 +1249,7 @@ test "byte vector initialized in inline function" {
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
if (builtin.cpu.arch == .aarch64_be and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest;
if (comptime builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .x86_64 and
builtin.cpu.features.isEnabled(@intFromEnum(std.Target.x86.Feature.avx512f)))
@@ -1370,6 +1375,7 @@ test "store packed vector element" {
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
if (builtin.cpu.arch == .aarch64_be and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest;
var v = @Vector(4, u1){ 1, 1, 1, 1 };
try expectEqual(@Vector(4, u1){ 1, 1, 1, 1 }, v);
@@ -1406,6 +1412,7 @@ test "store vector with memset" {
if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
if (builtin.cpu.arch == .aarch64_be and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest;
var a: [5]@Vector(2, i1) = undefined;
var b: [5]@Vector(2, u2) = undefined;

3
test/llvm_targets.zig
View File

@@ -225,7 +225,6 @@ const targets = [_]std.Target.Query{
.{ .cpu_arch = .riscv32, .os_tag = .linux, .abi = .gnu },
.{ .cpu_arch = .riscv32, .os_tag = .linux, .abi = .musl },
.{ .cpu_arch = .riscv32, .os_tag = .linux, .abi = .none },
.{ .cpu_arch = .riscv32, .os_tag = .linux, .abi = .ohos },
.{ .cpu_arch = .riscv32, .os_tag = .rtems, .abi = .none },
.{ .cpu_arch = .riscv32, .os_tag = .uefi, .abi = .none },
@@ -238,7 +237,6 @@ const targets = [_]std.Target.Query{
.{ .cpu_arch = .riscv64, .os_tag = .linux, .abi = .gnu },
.{ .cpu_arch = .riscv64, .os_tag = .linux, .abi = .musl },
.{ .cpu_arch = .riscv64, .os_tag = .linux, .abi = .none },
.{ .cpu_arch = .riscv64, .os_tag = .linux, .abi = .ohos },
.{ .cpu_arch = .riscv64, .os_tag = .netbsd, .abi = .none },
.{ .cpu_arch = .riscv64, .os_tag = .openbsd, .abi = .none },
.{ .cpu_arch = .riscv64, .os_tag = .rtems, .abi = .none },
@@ -326,7 +324,6 @@ const targets = [_]std.Target.Query{
.{ .cpu_arch = .x86, .os_tag = .linux, .abi = .gnu },
.{ .cpu_arch = .x86, .os_tag = .linux, .abi = .musl },
.{ .cpu_arch = .x86, .os_tag = .linux, .abi = .none },
.{ .cpu_arch = .x86, .os_tag = .linux, .abi = .ohos },
.{ .cpu_arch = .x86, .os_tag = .netbsd, .abi = .none },
.{ .cpu_arch = .x86, .os_tag = .openbsd, .abi = .none },
.{ .cpu_arch = .x86, .os_tag = .rtems, .abi = .none },

24
test/tests.zig
View File

@@ -291,6 +291,30 @@ const test_targets = blk: {
.link_libc = true,
},
.{
.target = .{
.cpu_arch = .aarch64_be,
.os_tag = .linux,
.abi = .none,
},
},
.{
.target = .{
.cpu_arch = .aarch64_be,
.os_tag = .linux,
.abi = .musl,
},
.link_libc = true,
},
.{
.target = .{
.cpu_arch = .aarch64_be,
.os_tag = .linux,
.abi = .gnu,
},
.link_libc = true,
},
.{
.target = .{
.cpu_arch = .arm,