zig

commit 4ed2c52fb7b3b6d541235b6e9096a6e72b99ca2a (tree)
parent e2e0b6272b98ef2ec810fbabcdc91a21e54a71a3
Author: Vexu <git@vexu.eu>
Date:   Fri, 30 Oct 2020 15:47:12 +0200

stage2: switch put swap condbr and block

condbr is noreturn so having the other way around caused
subsequent cases to be eliminated as dead

Diffstat:
M
src/astgen.zig
 | 
22
+++++++++-------------
M
src/codegen.zig
 | 
11
++++++++++-
M
src/main.zig
 | 
1
+

3 files changed, 20 insertions(+), 14 deletions(-)
diff --git a/src/astgen.zig b/src/astgen.zig
@@ -1733,32 +1733,28 @@ fn switchExpr(mod: *Module, scope: *Scope, rl: ResultLoc, switch_node: *ast.Node
             }
         }
 
-        const condbr = try addZIRInstSpecial(mod, &else_scope.base, case_src, zir.Inst.CondBr, .{
+        const condbr = try addZIRInstSpecial(mod, &case_scope.base, case_src, zir.Inst.CondBr, .{
             .condition = any_ok.?,
             .then_body = undefined, // populated below
             .else_body = undefined, // populated below
         }, .{});
-
-        try switchCaseExpr(mod, &case_scope.base, case_rl, block, case);
-        condbr.positionals.then_body = .{
+        const cond_block = try addZIRInstBlock(mod, &else_scope.base, case_src, .block, .{
             .instructions = try scope.arena().dupe(*zir.Inst, case_scope.instructions.items),
-        };
+        });
 
-        // reset to add the empty block
+        // reset cond_scope for then_body
         case_scope.instructions.items.len = 0;
-        const empty_block = try addZIRInstBlock(mod, &case_scope.base, case_src, .block, .{
-            .instructions = undefined, // populated below
-        });
-        condbr.positionals.else_body = .{
+        try switchCaseExpr(mod, &case_scope.base, case_rl, block, case);
+        condbr.positionals.then_body = .{
             .instructions = try scope.arena().dupe(*zir.Inst, case_scope.instructions.items),
         };
 
-        // reset to add a break to the empty block
+        // reset cond_scope for else_body
         case_scope.instructions.items.len = 0;
         _ = try addZIRInst(mod, &case_scope.base, case_src, zir.Inst.BreakVoid, .{
-            .block = empty_block,
+            .block = cond_block,
         }, .{});
-        empty_block.positionals.body = .{
+        condbr.positionals.else_body = .{
             .instructions = try scope.arena().dupe(*zir.Inst, case_scope.instructions.items),
         };
     }
diff --git a/src/codegen.zig b/src/codegen.zig
@@ -2033,8 +2033,17 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
         }
 
         fn genBoolOp(self: *Self, inst: *ir.Inst.BinOp) !MCValue {
+            if (inst.base.isUnused())
+                return MCValue.dead;
             switch (arch) {
-                else => return self.fail(inst.base.src, "TODO genBoolOp for {}", .{self.target.cpu.arch}),
+                .x86_64 => if (inst.base.tag == .booland) {
+                    // lhs AND rhs
+                    return try self.genX8664BinMath(&inst.base, inst.lhs, inst.rhs, 4, 0x20);
+                } else {
+                    // lhs OR rhs
+                    return try self.genX8664BinMath(&inst.base, inst.lhs, inst.rhs, 1, 0x08);
+                },
+                else => return self.fail(inst.base.src, "TODO implement sub for {}", .{self.target.cpu.arch}),
             }
         }
 
diff --git a/src/main.zig b/src/main.zig
@@ -2421,6 +2421,7 @@ pub fn cmdFmt(gpa: *Allocator, args: []const []const u8) !void {
     var stdin_flag: bool = false;
     var check_flag: bool = false;
     var input_files = ArrayList([]const u8).init(gpa);
+    defer input_files.deinit();
 
     {
         var i: usize = 0;