zig

commit 5bc35fa75bf62bc9a76305fc6bfc3530efba6aec (tree)
parent 2b7334c3a9c873a637f8d601ad9077d783058863
Author: serg <sergpolkin@gmail.com>
Date:   Sun, 16 Apr 2023 10:59:11 +0300

std.target.riscv: fix baseline_rv32 missing feature "32bit"

Diffstat:
M
lib/std/target/riscv.zig
 | 
1
+
M
tools/update_cpu_features.zig
 | 
2
+-

2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/lib/std/target/riscv.zig b/lib/std/target/riscv.zig
@@ -748,6 +748,7 @@ pub const cpu = struct {
         .name = "baseline_rv32",
         .llvm_name = null,
         .features = featureSet(&[_]Feature{
+            .@"32bit",
             .a,
             .c,
             .d,
diff --git a/tools/update_cpu_features.zig b/tools/update_cpu_features.zig
@@ -866,7 +866,7 @@ const llvm_targets = [_]LlvmTarget{
             .{
                 .llvm_name = null,
                 .zig_name = "baseline_rv32",
-                .features = &.{ "a", "c", "d", "f", "m" },
+                .features = &.{ "32bit", "a", "c", "d", "f", "m" },
             },
             .{
                 .llvm_name = null,