zig

commit 5bd27a2cb6ead1108e2e177f4e2730f31224925c (tree)
parent ae6df9e96749cdd7cd4f84245ce20cfb3d4d6354
Author: xdBronch <51252236+xdBronch@users.noreply.github.com>
Date:   Fri,  3 Nov 2023 02:56:26 -0400

dont assume apple chips are macos exclusive

Diffstat:
M
lib/std/zig/system/arm.zig
 | 
16
++++++++++++++++

1 file changed, 16 insertions(+), 0 deletions(-)
diff --git a/lib/std/zig/system/arm.zig b/lib/std/zig/system/arm.zig
@@ -111,6 +111,21 @@ pub const cpu_models = struct {
         E{ .part = 0xc01, .m64 = &A64.saphira },
     };
 
+    const Apple = [_]E{
+        E{ .part = 0x022, .m64 = &A64.apple_m1 },
+        E{ .part = 0x023, .m64 = &A64.apple_m1 },
+        E{ .part = 0x024, .m64 = &A64.apple_m1 },
+        E{ .part = 0x025, .m64 = &A64.apple_m1 },
+        E{ .part = 0x028, .m64 = &A64.apple_m1 },
+        E{ .part = 0x029, .m64 = &A64.apple_m1 },
+        E{ .part = 0x032, .m64 = &A64.apple_m2 },
+        E{ .part = 0x033, .m64 = &A64.apple_m2 },
+        E{ .part = 0x034, .m64 = &A64.apple_m2 },
+        E{ .part = 0x035, .m64 = &A64.apple_m2 },
+        E{ .part = 0x038, .m64 = &A64.apple_m2 },
+        E{ .part = 0x039, .m64 = &A64.apple_m2 },
+    };
+
     pub fn isKnown(core: CoreInfo, is_64bit: bool) ?*const Target.Cpu.Model {
         const models = switch (core.implementer) {
             0x41 => &ARM,
@@ -120,6 +135,7 @@ pub const cpu_models = struct {
             0x48 => &HiSilicon,
             0x50 => &Ampere,
             0x51 => &Qualcomm,
+            0x61 => &Apple,
             else => return null,
         };