zig

commit 5d260eb573132194e802680803f225404a06b00e (tree)
parent 2770f9a03464dee1e11134054598a6e07c30a6e4
Author: Koakuma <koachan@protonmail.com>
Date:   Mon,  2 May 2022 21:56:04 +0700

stage2: sparc64: Implement SPARCv9 subcc

Diffstat:
M
src/arch/sparc64/Emit.zig
 | 
4
+++-
M
src/arch/sparc64/bits.zig
 | 
8
++++++++

2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/src/arch/sparc64/Emit.zig b/src/arch/sparc64/Emit.zig
@@ -81,7 +81,7 @@ pub fn emitMir(
             .stx => try emit.mirArithmetic3Op(inst),
 
             .sub => try emit.mirArithmetic3Op(inst),
-            .subcc => @panic("TODO implement sparcv9 subcc"),
+            .subcc => try emit.mirArithmetic3Op(inst),
 
             .tcc => try emit.mirTrap(inst),
         }
@@ -169,6 +169,7 @@ fn mirArithmetic3Op(emit: *Emit, inst: Mir.Inst.Index) !void {
             .stw => try emit.writeInstruction(Instruction.stw(i13, rs1, imm, rd)),
             .stx => try emit.writeInstruction(Instruction.stx(i13, rs1, imm, rd)),
             .sub => try emit.writeInstruction(Instruction.sub(i13, rs1, imm, rd)),
+            .subcc => try emit.writeInstruction(Instruction.subcc(i13, rs1, imm, rd)),
             else => unreachable,
         }
     } else {
@@ -188,6 +189,7 @@ fn mirArithmetic3Op(emit: *Emit, inst: Mir.Inst.Index) !void {
             .stw => try emit.writeInstruction(Instruction.stw(Register, rs1, rs2, rd)),
             .stx => try emit.writeInstruction(Instruction.stx(Register, rs1, rs2, rd)),
             .sub => try emit.writeInstruction(Instruction.sub(Register, rs1, rs2, rd)),
+            .subcc => try emit.writeInstruction(Instruction.subcc(Register, rs1, rs2, rd)),
             else => unreachable,
         }
     }
diff --git a/src/arch/sparc64/bits.zig b/src/arch/sparc64/bits.zig
@@ -1261,6 +1261,14 @@ pub const Instruction = union(enum) {
         };
     }
 
+    pub fn subcc(comptime s2: type, rs1: Register, rs2: s2, rd: Register) Instruction {
+        return switch (s2) {
+            Register => format3a(0b10, 0b01_0100, rs1, rs2, rd),
+            i13 => format3b(0b10, 0b01_0100, rs1, rs2, rd),
+            else => unreachable,
+        };
+    }
+
     pub fn trap(comptime s2: type, cond: ICondition, ccr: CCR, rs1: Register, rs2: s2) Instruction {
         // Tcc instructions abuse the rd field to store the conditionals.
         return switch (s2) {