zig

commit 664e3e16fa8dd49ff97f78dcdbf4579ff7f652aa (tree)
parent 3ccf0fd4c2d024d696bdb1e71a0b36af38ad6bed
Author: David Rubin <daviru007@icloud.com>
Date:   Thu, 14 Mar 2024 18:29:24 -0700

riscv: add `cmp_eq` MIR instruction

this opens up the door for addition!

Diffstat:
M
src/arch/riscv64/CodeGen.zig
 | 
2
++
M
src/arch/riscv64/Emit.zig
 | 
6
++++++

2 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/src/arch/riscv64/CodeGen.zig b/src/arch/riscv64/CodeGen.zig
@@ -942,6 +942,8 @@ fn binOpRegister(
         },
     });
 
+    // generate the struct for OF checks
+
     return MCValue{ .register = dest_reg };
 }
 
diff --git a/src/arch/riscv64/Emit.zig b/src/arch/riscv64/Emit.zig
@@ -177,6 +177,10 @@ fn mirRType(emit: *Emit, inst: Mir.Inst.Index) !void {
         .add => try emit.writeInstruction(Instruction.add(r_type.rd, r_type.rs1, r_type.rs2)),
         .sub => try emit.writeInstruction(Instruction.sub(r_type.rd, r_type.rs1, r_type.rs2)),
         .cmp_gt => try emit.writeInstruction(Instruction.slt(r_type.rd, r_type.rs1, r_type.rs2)),
+        .cmp_eq => {
+            try emit.writeInstruction(Instruction.xor(r_type.rd, r_type.rs1, r_type.rs2));
+            try emit.writeInstruction(Instruction.sltiu(r_type.rd, r_type.rd, 1));
+        },
         else => unreachable,
     }
 }
@@ -459,6 +463,8 @@ fn instructionSize(emit: *Emit, inst: Mir.Inst.Index) usize {
 
         .abs => 12, // 3 * 4
 
+        .cmp_eq => 8,
+
         else => 4,
     };
 }