zig

commit 7747bf07c73a174dbd8c976dca8a94114c49349d (tree)
parent 00966b7258bdf56fe2cc653b30b4d4352d8fe14f
Author: Jakub Konka <kubkon@jakubkonka.com>
Date:   Thu, 18 Nov 2021 19:46:56 +0100

stage2: use correct register alias for mem operands

When loading/storing on the stack, use `registerAlias` to correctly
workout the size of the register and thus correctly select target
instruction.

Diffstat:
M
src/arch/x86_64/CodeGen.zig
 | 
8
++++----

1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/arch/x86_64/CodeGen.zig b/src/arch/x86_64/CodeGen.zig
@@ -1545,7 +1545,7 @@ fn genBinMathOpMir(
                     _ = try self.addInst(.{
                         .tag = mir_tag,
                         .ops = (Mir.Ops{
-                            .reg1 = dst_reg,
+                            .reg1 = registerAlias(dst_reg, @intCast(u32, abi_size)),
                             .reg2 = .ebp,
                             .flags = 0b01,
                         }).encode(),
@@ -1576,7 +1576,7 @@ fn genBinMathOpMir(
                     _ = try self.addInst(.{
                         .tag = mir_tag,
                         .ops = (Mir.Ops{
-                            .reg1 = src_reg,
+                            .reg1 = registerAlias(src_reg, @intCast(u32, abi_size)),
                             .reg2 = .ebp,
                             .flags = 0b10,
                         }).encode(),
@@ -2749,7 +2749,7 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro
             _ = try self.addInst(.{
                 .tag = .mov,
                 .ops = (Mir.Ops{
-                    .reg1 = reg,
+                    .reg1 = registerAlias(reg, @intCast(u32, abi_size)),
                     .reg2 = .ebp,
                     .flags = 0b10,
                 }).encode(),
@@ -2970,7 +2970,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
             _ = try self.addInst(.{
                 .tag = .mov,
                 .ops = (Mir.Ops{
-                    .reg1 = reg,
+                    .reg1 = registerAlias(reg, @intCast(u32, abi_size)),
                     .reg2 = .ebp,
                     .flags = 0b01,
                 }).encode(),