zig

commit 7d71e794dd22e4c2a38d3aafd4fc604b36d2ac5e (tree)
parent cb1ac0bb2fb95424118404160704d53a3ff2a2c0
Author: Alex Rønne Petersen <alex@alexrp.com>
Date:   Tue,  1 Oct 2024 06:37:25 +0200

std.Target: Fix Cpu.Model.generic() for arc, csky, and xtensa.

Only targets for which we don't source CPU models/features from LLVM should use
the fallback prong in this switch. Also make it exhaustive to catch similar
mistakes in the future.

Diffstat:
M
lib/std/Target.zig
 | 
7
++++++-

1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/lib/std/Target.zig b/lib/std/Target.zig
@@ -1526,10 +1526,12 @@ pub const Cpu = struct {
                 };
             };
             return switch (arch) {
+                .arc => &arc.cpu.generic,
                 .arm, .armeb, .thumb, .thumbeb => &arm.cpu.generic,
                 .aarch64, .aarch64_be => &aarch64.cpu.generic,
                 .avr => &avr.cpu.avr2,
                 .bpfel, .bpfeb => &bpf.cpu.generic,
+                .csky => &csky.cpu.generic,
                 .hexagon => &hexagon.cpu.generic,
                 .lanai => &lanai.cpu.generic,
                 .loongarch32 => &loongarch.cpu.generic_la32,
@@ -1555,8 +1557,11 @@ pub const Cpu = struct {
                 .ve => &ve.cpu.generic,
                 .wasm32, .wasm64 => &wasm.cpu.generic,
                 .xcore => &xcore.cpu.generic,
+                .xtensa => &xtensa.cpu.generic,
 
-                else => &S.generic_model,
+                .kalimba,
+                .spu_2,
+                => &S.generic_model,
             };
         }