zig

commit 8062bdba9aa2dd5c4f63106a952df5d75c4f4ccb (tree)
parent c50fb583073ccae245fae9018e09ef0c2d2211c2
Author: Alex Rønne Petersen <alex@alexrp.com>
Date:   Thu, 17 Oct 2024 01:49:27 +0200

std.Target: Use avr1 as the generic CPU model for avr.

avr2 remains the baseline CPU model.

Diffstat:
M
lib/std/Target.zig
 | 
3
++-

1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/lib/std/Target.zig b/lib/std/Target.zig
@@ -1800,7 +1800,7 @@ pub const Cpu = struct {
                 .arc => &arc.cpu.generic,
                 .arm, .armeb, .thumb, .thumbeb => &arm.cpu.generic,
                 .aarch64, .aarch64_be => &aarch64.cpu.generic,
-                .avr => &avr.cpu.avr2,
+                .avr => &avr.cpu.avr1,
                 .bpfel, .bpfeb => &bpf.cpu.generic,
                 .csky => &csky.cpu.generic,
                 .hexagon => &hexagon.cpu.generic,
@@ -1856,6 +1856,7 @@ pub const Cpu = struct {
                     .watchos => &aarch64.cpu.apple_s4,
                     else => generic(arch),
                 },
+                .avr => &avr.cpu.avr2,
                 .csky => &csky.cpu.ck810, // gcc/clang do not have a generic csky model.
                 .hexagon => &hexagon.cpu.hexagonv60, // gcc/clang do not have a generic hexagon model.
                 .lanai => &lanai.cpu.v11, // clang does not have a generic lanai model.