zig

commit 81ef502f08e966fb57c4313a9c7e9b6f9f55aa4a (tree)
parent 65c073b1475d38c4b8e004b4dd7624f7e41e3c99
Author: Alex Rønne Petersen <alex@alexrp.com>
Date:   Mon,  9 Feb 2026 23:54:12 +0100

generate_linux_syscalls: add hexagon abi name

Diffstat:
M
tools/generate_linux_syscalls.zig
 | 
3
++-

1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tools/generate_linux_syscalls.zig b/tools/generate_linux_syscalls.zig
@@ -73,6 +73,7 @@ const Abi = enum {
     nios2,
     or1k,
     riscv,
+    hexagon,
 };
 
 const __X32_SYSCALL_BIT: u32 = 0x40000000;
@@ -161,7 +162,7 @@ const architectures: []const Arch = &.{
     .{ .@"var" = "LoongArch64", .table = .generic, .abi = &.{ .common, .@"64" } },
     .{ .@"var" = "Arc", .table = .generic, .abi = &.{ .common, .@"32", .arc, .time32, .renameat, .stat64, .rlimit } },
     .{ .@"var" = "CSky", .table = .generic, .abi = &.{ .common, .@"32", .csky, .time32, .stat64, .rlimit } },
-    .{ .@"var" = "Hexagon", .table = .generic, .abi = &.{ .common, .@"32", .time32, .stat64, .rlimit, .renameat } },
+    .{ .@"var" = "Hexagon", .table = .generic, .abi = &.{ .common, .@"32", .hexagon, .time32, .stat64, .rlimit, .renameat } },
     .{ .@"var" = "OpenRisc", .table = .generic, .abi = &.{ .common, .@"32", .or1k, .time32, .stat64, .rlimit, .renameat } },
     // .{ .@"var" = "Nios2", .table = .generic, .abi = &.{ .common, .@"32", .nios2, .time32, .stat64, .rlimit, .renameat } },
     // .{ .@"var" = "Parisc", .table = .{ .specific = "arch/parisc/kernel/syscalls/syscall.tbl" }, .abi = &.{ .common, .@"32" } },