zig

commit 86853ba0a49579fdd8a41ac2c243075d8e51d83c (tree)
parent cf0f6dd17fc9c534b11c6a3f3f6e448702a9a93a
Author: Neel <ntamtam614@gmail.com>
Date:   Tue,  7 Apr 2026 12:24:13 -0500

Add RISC-V ABI register alias names for inline asm clobbers

Diffstat:
M
lib/std/builtin/assembly.zig
 | 
68
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
M
test/behavior/asm.zig
 | 
15
+++++++++++++++

2 files changed, 83 insertions(+), 0 deletions(-)
diff --git a/lib/std/builtin/assembly.zig b/lib/std/builtin/assembly.zig
@@ -682,6 +682,40 @@ pub const Clobbers = switch (@import("builtin").cpu.arch) {
         x30: bool = false,
         x31: bool = false,
 
+        // ABI aliases for integer registers
+        ra: bool = false,
+        sp: bool = false,
+        gp: bool = false,
+        tp: bool = false,
+        t0: bool = false,
+        t1: bool = false,
+        t2: bool = false,
+        s0: bool = false,
+        fp: bool = false,
+        s1: bool = false,
+        a0: bool = false,
+        a1: bool = false,
+        a2: bool = false,
+        a3: bool = false,
+        a4: bool = false,
+        a5: bool = false,
+        a6: bool = false,
+        a7: bool = false,
+        s2: bool = false,
+        s3: bool = false,
+        s4: bool = false,
+        s5: bool = false,
+        s6: bool = false,
+        s7: bool = false,
+        s8: bool = false,
+        s9: bool = false,
+        s10: bool = false,
+        s11: bool = false,
+        t3: bool = false,
+        t4: bool = false,
+        t5: bool = false,
+        t6: bool = false,
+
         fflags: bool = false,
         frm: bool = false,
 
@@ -718,6 +752,40 @@ pub const Clobbers = switch (@import("builtin").cpu.arch) {
         f30: bool = false,
         f31: bool = false,
 
+        // ABI aliases for float registers
+        ft0: bool = false,
+        ft1: bool = false,
+        ft2: bool = false,
+        ft3: bool = false,
+        ft4: bool = false,
+        ft5: bool = false,
+        ft6: bool = false,
+        ft7: bool = false,
+        fs0: bool = false,
+        fs1: bool = false,
+        fa0: bool = false,
+        fa1: bool = false,
+        fa2: bool = false,
+        fa3: bool = false,
+        fa4: bool = false,
+        fa5: bool = false,
+        fa6: bool = false,
+        fa7: bool = false,
+        fs2: bool = false,
+        fs3: bool = false,
+        fs4: bool = false,
+        fs5: bool = false,
+        fs6: bool = false,
+        fs7: bool = false,
+        fs8: bool = false,
+        fs9: bool = false,
+        fs10: bool = false,
+        fs11: bool = false,
+        ft8: bool = false,
+        ft9: bool = false,
+        ft10: bool = false,
+        ft11: bool = false,
+
         vtype: bool = false,
         vl: bool = false,
         vxsat: bool = false,
diff --git a/test/behavior/asm.zig b/test/behavior/asm.zig
@@ -246,3 +246,18 @@ test "extern output types (x86_64)" {
         try expect(u.x == 123);
     }
 }
+
+test "riscv abi register aliases as clobbers" {
+    if (!builtin.target.cpu.arch.isRISCV()) return error.SkipZigTest;
+    if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
+    if (builtin.zig_backend == .stage2_c and builtin.os.tag == .windows) return error.SkipZigTest;
+
+    if (!comptime builtin.cpu.arch.isRISCV()) return error.SkipZigTest;
+
+    // Verify that ABI alias names are accepted as clobbers for RISC-V.
+    asm volatile ("" ::: .{ .ra = true, .sp = true, .gp = true, .tp = true });
+    asm volatile ("" ::: .{ .a0 = true, .a1 = true, .a2 = true, .a3 = true, .a4 = true, .a5 = true, .a6 = true, .a7 = true });
+    asm volatile ("" ::: .{ .t0 = true, .t1 = true, .t2 = true, .t3 = true, .t4 = true, .t5 = true, .t6 = true });
+    asm volatile ("" ::: .{ .s0 = true, .fp = true, .s1 = true, .s2 = true, .s3 = true, .s4 = true, .s5 = true, .s6 = true, .s7 = true, .s8 = true, .s9 = true, .s10 = true, .s11 = true });
+    asm volatile ("" ::: .{ .fa0 = true, .fa1 = true, .ft0 = true, .fs0 = true });
+}