zig

commit 89df41e5d859fcd53863c9f707e8c697b794148c (tree)
parent 2bfc6d14d500dcaf66b8ee7d24637e25e3795a5e
Author: LemonBoy <thatlemon@gmail.com>
Date:   Tue,  6 Apr 2021 10:47:29 +0200

stage2: Default AVR generic cpu to avr2

The avr1 target is a very minimal subset of the AVR ISA, quoting the GCC
manual:

> This ISA is implemented by the minimal AVR core and supported for
> assembler only.

Default to avr2 as GCC and Clang do.

Diffstat:
M
lib/std/target.zig
 | 
2
+-

1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/std/target.zig b/lib/std/target.zig
@@ -1170,7 +1170,7 @@ pub const Target = struct {
                 return switch (arch) {
                     .arm, .armeb, .thumb, .thumbeb => &arm.cpu.generic,
                     .aarch64, .aarch64_be, .aarch64_32 => &aarch64.cpu.generic,
-                    .avr => &avr.cpu.avr1,
+                    .avr => &avr.cpu.avr2,
                     .bpfel, .bpfeb => &bpf.cpu.generic,
                     .hexagon => &hexagon.cpu.generic,
                     .mips, .mipsel => &mips.cpu.mips32,