zig

commit 8a478b4e9e06ac0e0a59fc575222cf075aa64bc4 (tree)
parent 5aa50bcbff7f6bee7217f5e6e3e358f47aa748c8
Author: Andrew Kelley <andrew@ziglang.org>
Date:   Tue, 15 Jul 2025 19:25:56 -0700

fix sparc ccr regs

Diffstat:
M
lib/std/builtin/assembly.zig
 | 
10
+++++++---

1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/lib/std/builtin/assembly.zig b/lib/std/builtin/assembly.zig
@@ -1004,13 +1004,17 @@ pub const Clobbers = switch (@import("builtin").cpu.arch) {
         /// addresses other than those derived from input pointer provenance.
         memory: bool = false,
 
-        xcc: bool = false,
-
         psr: bool = false,
-        ccr: bool = false,
         gsr: bool = false,
         y: bool = false,
 
+        /// asr2; v9+
+        ccr: bool = false,
+        /// Lower bits of `ccr`.
+        icc: bool = false,
+        /// Upper bits of `ccr`.
+        xcc: bool = false,
+
         g1: bool = false,
         g2: bool = false,
         g3: bool = false,