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Merge pull request #20870 from alexrp/target-cleanup-3

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`std.Target`: Remove more dead OS/architecture tags
This commit is contained in:
Andrew Kelley
2024-08-01 01:32:32 -07:00
committed by GitHub
parent f17f73b4fa 62a01851d9
commit 8f7cbaa4c0
21 changed files with 42 additions and 110 deletions
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4
lib/compiler/aro/aro/Compilation.zig vendored
View File

@@ -363,7 +363,7 @@ fn generateSystemDefines(comp: *Compilation, w: anytype) !void {
\\#define __sparc_v9__ 1
\\
),
.sparc, .sparcel => try w.writeAll(
.sparc => try w.writeAll(
\\#define __sparc__ 1
\\#define __sparc 1
\\
@@ -534,7 +534,7 @@ pub fn generateBuiltinMacros(comp: *Compilation, system_defines_mode: SystemDefi
if (system_defines_mode == .include_system_defines) {
try buf.appendSlice(
\\#define __VERSION__ "Aro
\\#define __VERSION__ "Aro
++ @import("../backend.zig").version_str ++ "\"\n" ++
\\#define __Aro__
\\

2
lib/compiler/aro/aro/Driver/GCCDetector.zig vendored
View File

@@ -376,7 +376,7 @@ fn collectLibDirsAndTriples(
biarch_libdirs.appendSliceAssumeCapacity(&RISCV32LibDirs);
biarch_triple_aliases.appendSliceAssumeCapacity(&RISCV32Triples);
},
.sparc, .sparcel => {
.sparc => {
lib_dirs.appendSliceAssumeCapacity(&SPARCv8LibDirs);
triple_aliases.appendSliceAssumeCapacity(&SPARCv8Triples);
biarch_libdirs.appendSliceAssumeCapacity(&SPARCv9LibDirs);

18
lib/compiler/aro/aro/target.zig vendored
View File

@@ -53,13 +53,12 @@ pub fn intPtrType(target: std.Target) Type {
.xcore,
.hexagon,
.m68k,
.spir,
.spirv32,
.arc,
.avr,
=> return .{ .specifier = .int },
.sparc, .sparcel => switch (target.os.tag) {
.sparc => switch (target.os.tag) {
.netbsd, .openbsd => {},
else => return .{ .specifier = .int },
},
@@ -133,7 +132,7 @@ pub fn defaultFunctionAlignment(target: std.Target) u8 {
return switch (target.cpu.arch) {
.arm, .armeb => 4,
.aarch64, .aarch64_be => 4,
.sparc, .sparcel, .sparc64 => 4,
.sparc, .sparc64 => 4,
.riscv64 => 2,
else => 1,
};
@@ -427,7 +426,7 @@ pub fn ldEmulationOption(target: std.Target, arm_endianness: ?std.builtin.Endian
.powerpc64le => "elf64lppc",
.riscv32 => "elf32lriscv",
.riscv64 => "elf64lriscv",
.sparc, .sparcel => "elf32_sparc",
.sparc => "elf32_sparc",
.sparc64 => "elf64_sparc",
.loongarch32 => "elf32loongarch",
.loongarch64 => "elf64loongarch",
@@ -467,13 +466,11 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
.powerpcle,
.riscv32,
.sparc,
.sparcel,
.thumb,
.thumbeb,
.x86,
.xcore,
.nvptx,
.spir,
.kalimba,
.lanai,
.wasm32,
@@ -487,7 +484,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
.aarch64_be => copy.cpu.arch = .armeb,
.nvptx64 => copy.cpu.arch = .nvptx,
.wasm64 => copy.cpu.arch = .wasm32,
.spir64 => copy.cpu.arch = .spir,
.spirv64 => copy.cpu.arch = .spirv32,
.loongarch64 => copy.cpu.arch = .loongarch32,
.mips64 => copy.cpu.arch = .mips,
@@ -513,7 +509,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
.lanai,
.m68k,
.msp430,
.sparcel,
.spu_2,
.xcore,
.xtensa,
@@ -526,7 +521,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
.bpfel,
.nvptx64,
.wasm64,
.spir64,
.spirv64,
.loongarch64,
.mips64,
@@ -550,7 +544,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
.powerpcle => copy.cpu.arch = .powerpc64le,
.riscv32 => copy.cpu.arch = .riscv64,
.sparc => copy.cpu.arch = .sparc64,
.spir => copy.cpu.arch = .spir64,
.spirv32 => copy.cpu.arch = .spirv64,
.thumb => copy.cpu.arch = .aarch64,
.thumbeb => copy.cpu.arch = .aarch64_be,
@@ -597,7 +590,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
.riscv64 => "riscv64",
.sparc => "sparc",
.sparc64 => "sparc64",
.sparcel => "sparcel",
.s390x => "s390x",
.thumb => "thumb",
.thumbeb => "thumbeb",
@@ -607,8 +599,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
.xtensa => "xtensa",
.nvptx => "nvptx",
.nvptx64 => "nvptx64",
.spir => "spir",
.spir64 => "spir64",
.spirv32 => "spirv32",
.spirv64 => "spirv64",
.kalimba => "kalimba",
@@ -624,8 +614,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
const llvm_os = switch (target.os.tag) {
.freestanding => "unknown",
.ananas => "ananas",
.cloudabi => "cloudabi",
.dragonfly => "dragonfly",
.freebsd => "freebsd",
.fuchsia => "fuchsia",

1
lib/compiler/aro/aro/toolchains/Linux.zig vendored
View File

@@ -357,7 +357,6 @@ fn getOSLibDir(target: std.Target) []const u8 {
.powerpc,
.powerpcle,
.sparc,
.sparcel,
=> return "lib32",
else => {},
}

2
lib/compiler_rt/atomics.zig
View File

@@ -30,7 +30,7 @@ const largest_atomic_size = switch (arch) {
// On SPARC systems that lacks CAS and/or swap instructions, the only
// available atomic operation is a test-and-set (`ldstub`), so we force
// every atomic memory access to go through the lock.
.sparc, .sparcel => if (cpu.features.featureSetHas(.hasleoncasa)) @sizeOf(usize) else 0,
.sparc => if (cpu.features.featureSetHas(.hasleoncasa)) @sizeOf(usize) else 0,
// XXX: On x86/x86_64 we could check the presence of cmpxchg8b/cmpxchg16b
// and set this parameter accordingly.

2
lib/compiler_rt/clear_cache.zig
View File

@@ -41,7 +41,7 @@ fn clear_cache(start: usize, end: usize) callconv(.C) void {
else => false,
};
const sparc = switch (arch) {
.sparc, .sparc64, .sparcel => true,
.sparc, .sparc64 => true,
else => false,
};
const apple = switch (os) {

60
lib/std/Target.zig
View File

@@ -17,8 +17,6 @@ pub const Os = struct {
pub const Tag = enum {
freestanding,
ananas,
cloudabi,
dragonfly,
freebsd,
fuchsia,
@@ -140,8 +138,6 @@ pub const Os = struct {
pub inline fn getVersionRangeTag(tag: Tag) @typeInfo(TaggedVersionRange).Union.tag_type.? {
return switch (tag) {
.freestanding,
.ananas,
.cloudabi,
.fuchsia,
.ps3,
.zos,
@@ -202,7 +198,7 @@ pub const Os = struct {
.mips, .mipsel, .mips64, .mips64el => "mips",
.powerpc, .powerpcle, .powerpc64, .powerpc64le => "powerpc",
.riscv32, .riscv64 => "riscv",
.sparc, .sparcel, .sparc64 => "sparc",
.sparc, .sparc64 => "sparc",
.x86, .x86_64 => "x86",
else => @tagName(arch),
},
@@ -373,8 +369,6 @@ pub const Os = struct {
pub fn default(tag: Tag, arch: Cpu.Arch) VersionRange {
return switch (tag) {
.freestanding,
.ananas,
.cloudabi,
.fuchsia,
.ps3,
.zos,
@@ -560,8 +554,6 @@ pub const Os = struct {
.linux,
.windows,
.freestanding,
.ananas,
.cloudabi,
.fuchsia,
.ps3,
.zos,
@@ -667,8 +659,6 @@ pub const Abi = enum {
pub fn default(arch: Cpu.Arch, os: Os) Abi {
return if (arch.isWasm()) .musl else switch (os.tag) {
.freestanding,
.ananas,
.cloudabi,
.dragonfly,
.ps3,
.zos,
@@ -1018,7 +1008,6 @@ pub const Cpu = struct {
riscv64,
sparc,
sparc64,
sparcel,
s390x,
thumb,
thumbeb,
@@ -1028,8 +1017,6 @@ pub const Cpu = struct {
xtensa,
nvptx,
nvptx64,
spir,
spir64,
spirv,
spirv32,
spirv64,
@@ -1043,12 +1030,17 @@ pub const Cpu = struct {
// LLVM tags deliberately omitted:
// - aarch64_32
// - r600
// - sparcel
// - tce
// - tcele
// - le32
// - le64
// - amdil
// - amdil64
// - hsail
// - hsail64
// - spir
// - spir64
// - shave
// - renderscript32
// - renderscript64
@@ -1122,7 +1114,7 @@ pub const Cpu = struct {
pub inline fn isSPARC(arch: Arch) bool {
return switch (arch) {
.sparc, .sparcel, .sparc64 => true,
.sparc, .sparc64 => true,
else => false,
};
}
@@ -1172,14 +1164,12 @@ pub const Cpu = struct {
.powerpc, .powerpcle => .PPC,
.riscv32 => .RISCV,
.sparc => .SPARC,
.sparcel => .SPARC,
.thumb => .ARM,
.thumbeb => .ARM,
.x86 => .@"386",
.xcore => .XCORE,
.xtensa => .XTENSA,
.nvptx => .NONE,
.spir => .NONE,
.kalimba => .CSR_KALIMBA,
.lanai => .LANAI,
.wasm32 => .NONE,
@@ -1192,7 +1182,6 @@ pub const Cpu = struct {
.riscv64 => .RISCV,
.x86_64 => .X86_64,
.nvptx64 => .NONE,
.spir64 => .NONE,
.wasm64 => .NONE,
.amdgcn => .AMDGPU,
.bpfel => .BPF,
@@ -1225,14 +1214,12 @@ pub const Cpu = struct {
.powerpc, .powerpcle => .POWERPC,
.riscv32 => .RISCV32,
.sparc => .Unknown,
.sparcel => .Unknown,
.thumb => .Thumb,
.thumbeb => .Thumb,
.x86 => .I386,
.xcore => .Unknown,
.xtensa => .Unknown,
.nvptx => .Unknown,
.spir => .Unknown,
.kalimba => .Unknown,
.lanai => .Unknown,
.wasm32 => .Unknown,
@@ -1245,7 +1232,6 @@ pub const Cpu = struct {
.riscv64 => .RISCV64,
.x86_64 => .X64,
.nvptx64 => .Unknown,
.spir64 => .Unknown,
.wasm64 => .Unknown,
.amdgcn => .Unknown,
.bpfel => .Unknown,
@@ -1279,7 +1265,6 @@ pub const Cpu = struct {
.msp430,
.nvptx,
.nvptx64,
.sparcel,
.powerpcle,
.powerpc64le,
.riscv32,
@@ -1290,8 +1275,6 @@ pub const Cpu = struct {
.wasm64,
.xcore,
.thumb,
.spir,
.spir64,
.ve,
.spu_2,
// GPU bitness is opaque. For now, assume little endian.
@@ -1348,7 +1331,7 @@ pub const Cpu = struct {
.powerpc, .powerpcle, .powerpc64, .powerpc64le => "powerpc",
.amdgcn => "amdgpu",
.riscv32, .riscv64 => "riscv",
.sparc, .sparc64, .sparcel => "sparc",
.sparc, .sparc64 => "sparc",
.s390x => "s390x",
.x86, .x86_64 => "x86",
.nvptx, .nvptx64 => "nvptx",
@@ -1375,7 +1358,7 @@ pub const Cpu = struct {
.powerpc, .powerpcle, .powerpc64, .powerpc64le => &powerpc.all_features,
.amdgcn => &amdgpu.all_features,
.riscv32, .riscv64 => &riscv.all_features,
.sparc, .sparc64, .sparcel => &sparc.all_features,
.sparc, .sparc64 => &sparc.all_features,
.spirv32, .spirv64 => &spirv.all_features,
.s390x => &s390x.all_features,
.x86, .x86_64 => &x86.all_features,
@@ -1405,7 +1388,7 @@ pub const Cpu = struct {
.powerpc, .powerpcle, .powerpc64, .powerpc64le => comptime allCpusFromDecls(powerpc.cpu),
.amdgcn => comptime allCpusFromDecls(amdgpu.cpu),
.riscv32, .riscv64 => comptime allCpusFromDecls(riscv.cpu),
.sparc, .sparc64, .sparcel => comptime allCpusFromDecls(sparc.cpu),
.sparc, .sparc64 => comptime allCpusFromDecls(sparc.cpu),
.spirv32, .spirv64 => comptime allCpusFromDecls(spirv.cpu),
.s390x => comptime allCpusFromDecls(s390x.cpu),
.x86, .x86_64 => comptime allCpusFromDecls(x86.cpu),
@@ -1497,7 +1480,7 @@ pub const Cpu = struct {
.riscv32 => &riscv.cpu.generic_rv32,
.riscv64 => &riscv.cpu.generic_rv64,
.spirv32, .spirv64 => &spirv.cpu.generic,
.sparc, .sparcel => &sparc.cpu.generic,
.sparc => &sparc.cpu.generic,
.sparc64 => &sparc.cpu.v9, // 64-bit SPARC needs v9 as the baseline
.s390x => &s390x.cpu.generic,
.x86 => &x86.cpu.i386,
@@ -1519,7 +1502,7 @@ pub const Cpu = struct {
.x86 => &x86.cpu.pentium4,
.nvptx, .nvptx64 => &nvptx.cpu.sm_20,
.s390x => &s390x.cpu.arch8,
.sparc, .sparcel => &sparc.cpu.v8,
.sparc => &sparc.cpu.v8,
.loongarch64 => &loongarch.cpu.loongarch64,
else => generic(arch),
@@ -1704,7 +1687,6 @@ pub const DynamicLinker = struct {
.linux => switch (cpu.arch) {
.x86,
.sparc,
.sparcel,
=> init("/lib/ld-linux.so.2"),
.aarch64 => init("/lib/ld-linux-aarch64.so.1"),
@@ -1773,8 +1755,6 @@ pub const DynamicLinker = struct {
.msp430,
.amdgcn,
.xcore,
.spir,
.spir64,
.kalimba,
.lanai,
.ve,
@@ -1811,8 +1791,6 @@ pub const DynamicLinker = struct {
// TODO go over each item in this list and either move it to the above list, or
// implement the standard dynamic linker path code for it.
.ananas,
.cloudabi,
.fuchsia,
.ps3,
.zos,
@@ -1865,13 +1843,11 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
.powerpc,
.powerpcle,
.riscv32,
.sparcel,
.thumb,
.thumbeb,
.x86,
.xcore,
.nvptx,
.spir,
.kalimba,
.lanai,
.wasm32,
@@ -1890,7 +1866,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
.riscv64,
.x86_64,
.nvptx64,
.spir64,
.wasm64,
.amdgcn,
.bpfel,
@@ -1927,7 +1902,6 @@ pub fn stackAlignment(target: Target) u16 {
.mips,
.mipsel,
.sparc,
.sparcel,
=> 8,
.aarch64,
.aarch64_be,
@@ -2088,7 +2062,6 @@ pub fn c_type_bit_size(target: Target, c_type: CType) u16 {
.s390x,
.sparc,
.sparc64,
.sparcel,
.wasm32,
.wasm64,
.loongarch32,
@@ -2111,7 +2084,6 @@ pub fn c_type_bit_size(target: Target, c_type: CType) u16 {
.solaris,
.illumos,
.haiku,
.ananas,
.fuchsia,
.minix,
=> switch (target.cpu.arch) {
@@ -2195,7 +2167,6 @@ pub fn c_type_bit_size(target: Target, c_type: CType) u16 {
.mips64el,
.sparc,
.sparc64,
.sparcel,
.wasm32,
.wasm64,
.loongarch32,
@@ -2307,7 +2278,6 @@ pub fn c_type_bit_size(target: Target, c_type: CType) u16 {
.longdouble => return 80,
},
.cloudabi,
.ps3,
.zos,
.rtems,
@@ -2375,7 +2345,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {
.xcore,
.dxil,
.loongarch32,
.spir,
.spirv32,
.kalimba,
.ve,
@@ -2392,13 +2361,11 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {
.mips,
.mipsel,
.sparc,
.sparcel,
.sparc64,
.lanai,
.nvptx,
.nvptx64,
.s390x,
.spir64,
.spirv64,
=> 8,
@@ -2483,7 +2450,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {
.xcore,
.dxil,
.loongarch32,
.spir,
.spirv32,
.kalimba,
.ve,
@@ -2507,13 +2473,11 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {
.mips,
.mipsel,
.sparc,
.sparcel,
.sparc64,
.lanai,
.nvptx,
.nvptx64,
.s390x,
.spir64,
.spirv64,
=> 8,

1
lib/std/atomic.zig
View File

@@ -478,7 +478,6 @@ pub const cache_line = switch (builtin.cpu.arch) {
.riscv32,
.riscv64,
.sparc,
.sparcel,
.sparc64,
=> 32,

2
lib/std/builtin.zig
View File

@@ -615,7 +615,7 @@ pub const VaList = switch (builtin.cpu.arch) {
else => VaListPowerPc,
},
.powerpc64, .powerpc64le => *u8,
.sparc, .sparcel, .sparc64 => *anyopaque,
.sparc, .sparc64 => *anyopaque,
.spirv32, .spirv64 => *anyopaque,
.s390x => VaListS390x,
.wasm32, .wasm64 => *anyopaque,

6
lib/std/c.zig
View File

@@ -5779,7 +5779,7 @@ pub const ucontext_t = switch (native_os) {
.x86 => 4,
.mips, .mipsel, .mips64, .mips64el => 14,
.arm, .armeb, .thumb, .thumbeb => 1,
.sparc, .sparcel, .sparc64 => if (@sizeOf(usize) == 4) 43 else 8,
.sparc, .sparc64 => if (@sizeOf(usize) == 4) 43 else 8,
else => 0,
}
]u32,
@@ -6821,7 +6821,7 @@ pub const pthread_key_t = switch (native_os) {
pub const padded_pthread_spin_t = switch (native_os) {
.netbsd => switch (builtin.cpu.arch) {
.x86, .x86_64 => u32,
.sparc, .sparcel, .sparc64 => u32,
.sparc, .sparc64 => u32,
else => pthread_spin_t,
},
else => void,
@@ -6834,7 +6834,7 @@ pub const pthread_spin_t = switch (native_os) {
.powerpc, .powerpc64, .powerpc64le => i32,
.x86, .x86_64 => u8,
.arm, .armeb, .thumb, .thumbeb => i32,
.sparc, .sparcel, .sparc64 => u8,
.sparc, .sparc64 => u8,
.riscv32, .riscv64 => u32,
else => @compileError("undefined pthread_spin_t for this arch"),
},

4
lib/std/os/linux.zig
View File

@@ -2496,7 +2496,7 @@ pub const E = switch (native_arch) {
pub const init = errnoFromSyscall;
},
.sparc, .sparcel, .sparc64 => enum(u16) {
.sparc, .sparc64 => enum(u16) {
/// No error occurred.
SUCCESS = 0,
@@ -4843,7 +4843,6 @@ pub const MINSIGSTKSZ = switch (native_arch) {
=> 2048,
.loongarch64,
.sparc,
.sparcel,
.sparc64,
=> 4096,
.aarch64,
@@ -4880,7 +4879,6 @@ pub const SIGSTKSZ = switch (native_arch) {
.aarch64_be,
.loongarch64,
.sparc,
.sparcel,
.sparc64,
=> 16384,
.powerpc64,

1
lib/std/os/linux/ioctl.zig
View File

@@ -11,7 +11,6 @@ const bits = switch (@import("builtin").cpu.arch) {
.powerpc64le,
.sparc,
.sparc64,
.sparcel,
=> .{ .size = 13, .dir = 3, .none = 1, .read = 2, .write = 4 },
else => .{ .size = 14, .dir = 2, .none = 0, .read = 2, .write = 1 },
};

3
src/Type.zig
View File

@@ -1602,7 +1602,6 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 {
.amdgcn,
.riscv32,
.sparc,
.sparcel,
.s390x,
.lanai,
.wasm32,
@@ -1647,11 +1646,9 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 {
.csky,
.arc,
.m68k,
.spir,
.kalimba,
.spirv,
.spirv32,
.spir64,
.ve,
.spirv64,
.dxil,

3
src/Zcu.zig
View File

@@ -3248,12 +3248,10 @@ pub fn atomicPtrAlignment(
.powerpcle,
.riscv32,
.sparc,
.sparcel,
.thumb,
.thumbeb,
.x86,
.xcore,
.spir,
.kalimba,
.lanai,
.wasm32,
@@ -3275,7 +3273,6 @@ pub fn atomicPtrAlignment(
.riscv64,
.sparc64,
.s390x,
.spir64,
.wasm64,
.ve,
.spirv64,

15
src/codegen/llvm.zig
View File

@@ -69,7 +69,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
.riscv64 => "riscv64",
.sparc => "sparc",
.sparc64 => "sparc64",
.sparcel => "sparcel",
.s390x => "s390x",
.thumb => "thumb",
.thumbeb => "thumbeb",
@@ -79,8 +78,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
.xtensa => "xtensa",
.nvptx => "nvptx",
.nvptx64 => "nvptx64",
.spir => "spir",
.spir64 => "spir64",
.spirv => "spirv",
.spirv32 => "spirv32",
.spirv64 => "spirv64",
@@ -136,8 +133,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
.opencl,
.glsl450,
.plan9,
.ananas,
.cloudabi,
.minix,
.contiki,
.other,
@@ -208,8 +203,6 @@ pub fn targetOs(os_tag: std.Target.Os.Tag) llvm.OSType {
.opencl,
.glsl450,
.plan9,
.ananas,
.cloudabi,
.minix,
.contiki,
=> .UnknownOS,
@@ -282,7 +275,6 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType {
.riscv64 => .riscv64,
.sparc => .sparc,
.sparc64 => .sparcv9, // In LLVM, sparc64 == sparcv9.
.sparcel => .sparcel,
.s390x => .systemz,
.thumb => .thumb,
.thumbeb => .thumbeb,
@@ -292,8 +284,6 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType {
.xtensa => .xtensa,
.nvptx => .nvptx,
.nvptx64 => .nvptx64,
.spir => .spir,
.spir64 => .spir64,
.spirv => .spirv,
.spirv32 => .spirv32,
.spirv64 => .spirv64,
@@ -473,7 +463,6 @@ const DataLayoutBuilder = struct {
.powerpcle,
.riscv32,
.sparc,
.sparcel,
.thumb,
.thumbeb,
.xtensa,
@@ -12008,7 +11997,7 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
llvm.LLVMInitializeRISCVAsmPrinter();
llvm.LLVMInitializeRISCVAsmParser();
},
.sparc, .sparc64, .sparcel => {
.sparc, .sparc64 => {
llvm.LLVMInitializeSparcTarget();
llvm.LLVMInitializeSparcTargetInfo();
llvm.LLVMInitializeSparcTargetMC();
@@ -12095,8 +12084,6 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
},
// LLVM backends that have no initialization functions.
.spir,
.spir64,
.spirv,
.spirv32,
.spirv64,

15
src/glibc.zig
View File

@@ -122,6 +122,17 @@ pub fn loadMetaData(gpa: Allocator, contents: []const u8) LoadMetaDataError!*ABI
return error.ZigInstallationCorrupt;
};
const arch_tag = std.meta.stringToEnum(std.Target.Cpu.Arch, arch_name) orelse {
// TODO: Remove this on the next glibc abilists update.
if (mem.eql(u8, arch_name, "sparcel")) {
targets[i] = .{
.arch = .sparc,
.os = .linux,
.abi = .gnu,
};
continue;
}
log.err("abilists: unrecognized arch: '{s}'", .{arch_name});
return error.ZigInstallationCorrupt;
};
@@ -394,7 +405,7 @@ fn start_asm_path(comp: *Compilation, arena: Allocator, basename: []const u8) ![
const arch = comp.getTarget().cpu.arch;
const is_ppc = arch == .powerpc or arch == .powerpc64 or arch == .powerpc64le;
const is_aarch64 = arch == .aarch64 or arch == .aarch64_be;
const is_sparc = arch == .sparc or arch == .sparcel or arch == .sparc64;
const is_sparc = arch == .sparc or arch == .sparc64;
const is_64 = comp.getTarget().ptrBitWidth() == 64;
const s = path.sep_str;
@@ -532,7 +543,7 @@ fn add_include_dirs_arch(
const is_x86 = arch == .x86 or arch == .x86_64;
const is_aarch64 = arch == .aarch64 or arch == .aarch64_be;
const is_ppc = arch == .powerpc or arch == .powerpc64 or arch == .powerpc64le;
const is_sparc = arch == .sparc or arch == .sparcel or arch == .sparc64;
const is_sparc = arch == .sparc or arch == .sparc64;
const is_64 = target.ptrBitWidth() == 64;
const s = path.sep_str;

2
src/link/Elf.zig
View File

@@ -4901,7 +4901,7 @@ fn getLDMOption(target: std.Target) ?[]const u8 {
.powerpc => return "elf32ppclinux",
.powerpc64 => return "elf64ppc",
.powerpc64le => return "elf64lppc",
.sparc, .sparcel => return "elf32_sparc",
.sparc => return "elf32_sparc",
.sparc64 => return "elf64_sparc",
.mips => return "elf32btsmip",
.mipsel => return "elf32ltsmip",

2
src/link/Plan9/aout.zig
View File

@@ -110,7 +110,7 @@ pub const R_MAGIC = _MAGIC(HDR_MAGIC, 28); // arm64
pub fn magicFromArch(arch: std.Target.Cpu.Arch) !u32 {
return switch (arch) {
.x86 => I_MAGIC,
.sparc => K_MAGIC, // TODO should sparc64 and sparcel go here?
.sparc => K_MAGIC, // TODO should sparc64 go here?
.mips => V_MAGIC,
.arm => E_MAGIC,
.aarch64 => R_MAGIC,

6
src/target.zig
View File

@@ -138,7 +138,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {
.riscv64,
.sparc,
.sparc64,
.sparcel,
.s390x,
.thumb,
.thumbeb,
@@ -148,8 +147,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {
.xtensa,
.nvptx,
.nvptx64,
.spir,
.spir64,
.spirv,
.spirv32,
.spirv64,
@@ -410,7 +407,7 @@ pub fn defaultFunctionAlignment(target: std.Target) Alignment {
return switch (target.cpu.arch) {
.arm, .armeb => .@"4",
.aarch64, .aarch64_be => .@"4",
.sparc, .sparcel, .sparc64 => .@"4",
.sparc, .sparc64 => .@"4",
.riscv64 => .@"2",
else => .@"1",
};
@@ -425,7 +422,6 @@ pub fn minFunctionAlignment(target: std.Target) Alignment {
.riscv32,
.riscv64,
.sparc,
.sparcel,
.sparc64,
=> .@"2",
else => .@"1",

1
test/behavior/align.zig
View File

@@ -95,7 +95,6 @@ test "alignment and size of structs with 128-bit fields" {
.amdgcn,
.riscv32,
.sparc,
.sparcel,
.s390x,
.lanai,
.wasm32,

2
test/llvm_targets.zig
View File

@@ -87,8 +87,6 @@ const targets = [_]std.Target.Query{
.{ .cpu_arch = .sparc, .os_tag = .freestanding, .abi = .none },
.{ .cpu_arch = .sparc, .os_tag = .linux, .abi = .gnu },
.{ .cpu_arch = .sparc, .os_tag = .linux, .abi = .none },
.{ .cpu_arch = .sparcel, .os_tag = .freestanding, .abi = .none },
.{ .cpu_arch = .sparcel, .os_tag = .linux, .abi = .gnu },
.{ .cpu_arch = .sparc64, .os_tag = .freestanding, .abi = .none },
.{ .cpu_arch = .sparc64, .os_tag = .linux, .abi = .gnu },
//.{ .cpu_arch = .spirv32, .os_tag = .opencl, .abi = .none },