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x86_64: fix undersized vector binary operations

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This commit is contained in:
Jacob Young
2023-10-08 01:28:17 -04:00
parent f6e027da32
commit 9fc9235ac8
2 changed files with 10 additions and 3 deletions
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10
src/arch/x86_64/CodeGen.zig
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@@ -7733,7 +7733,10 @@ fn genBinOp(
mir_tag,
dst_reg,
lhs_reg,
src_mcv.mem(Memory.PtrSize.fromSize(abi_size)),
src_mcv.mem(switch (lhs_ty.zigTypeTag(mod)) {
else => Memory.PtrSize.fromSize(abi_size),
.Vector => Memory.PtrSize.fromBitSize(dst_reg.bitSize()),
}),
) else try self.asmRegisterRegisterRegister(
mir_tag,
dst_reg,
@@ -7748,7 +7751,10 @@ fn genBinOp(
if (src_mcv.isMemory()) try self.asmRegisterMemory(
mir_tag,
dst_reg,
src_mcv.mem(Memory.PtrSize.fromSize(abi_size)),
src_mcv.mem(switch (lhs_ty.zigTypeTag(mod)) {
else => Memory.PtrSize.fromSize(abi_size),
.Vector => Memory.PtrSize.fromBitSize(dst_reg.bitSize()),
}),
) else try self.asmRegisterRegister(
mir_tag,
dst_reg,

3
test/behavior/maximum_minimum.zig
View File

@@ -276,7 +276,8 @@ test "@min/@max notices bounds from vector types when element of comptime-known
if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
if (builtin.zig_backend == .stage2_x86_64 and
!comptime std.Target.x86.featureSetHas(builtin.cpu.features, .sse4_1)) return error.SkipZigTest;
var x: @Vector(2, u32) = .{ 1_000_000, 12345 };
const y: @Vector(2, u16) = .{ 10, undefined };