zig

commit a2ab2fb9b080e233e1de2cb1ef74bdbc9476acb9 (tree)
parent c52ca0b1780c2865cb0c242cb2f1a397766e6ce8
Author: joachimschmidt557 <joachim.schmidt557@outlook.com>
Date:   Wed, 30 Dec 2020 19:54:34 +0100

stage2 ARM: Add simple tests for conditional branching

Diffstat:
M
test/stage2/arm.zig
 | 
62
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

1 file changed, 62 insertions(+), 0 deletions(-)
diff --git a/test/stage2/arm.zig b/test/stage2/arm.zig
@@ -282,4 +282,66 @@ pub fn addCases(ctx: *TestContext) !void {
             "123456",
         );
     }
+
+    {
+        var case = ctx.exe("if statements", linux_arm);
+        // Simple if statement in assert
+        case.addCompareOutput(
+            \\export fn _start() noreturn {
+            \\    var x: u32 = 123;
+            \\    var y: u32 = 42;
+            \\    assert(x > y);
+            \\    exit();
+            \\}
+            \\
+            \\fn assert(ok: bool) void {
+            \\    if (!ok) unreachable;
+            \\}
+            \\
+            \\fn exit() noreturn {
+            \\    asm volatile ("svc #0"
+            \\        :
+            \\        : [number] "{r7}" (1),
+            \\          [arg1] "{r0}" (0)
+            \\        : "memory"
+            \\    );
+            \\    unreachable;
+            \\}
+        ,
+            "",
+        );
+    }
+
+    {
+        var case = ctx.exe("while loops", linux_arm);
+        // Simple while loop with assert
+        case.addCompareOutput(
+            \\export fn _start() noreturn {
+            \\    var x: u32 = 2020;
+            \\    var i: u32 = 0;
+            \\    while (x > 0) {
+            \\        x -= 2;
+            \\        i += 1;
+            \\    }
+            \\    assert(i == 1010);
+            \\    exit();
+            \\}
+            \\
+            \\fn assert(ok: bool) void {
+            \\    if (!ok) unreachable;
+            \\}
+            \\
+            \\fn exit() noreturn {
+            \\    asm volatile ("svc #0"
+            \\        :
+            \\        : [number] "{r7}" (1),
+            \\          [arg1] "{r0}" (0)
+            \\        : "memory"
+            \\    );
+            \\    unreachable;
+            \\}
+        ,
+            "",
+        );
+    }
 }