commit a30688ef2a136c5a127c706880e8389b9b32e5be (tree)
parent 2a00df9c091498268b58dd671f646a5590439b7a
Author: Koakuma <koachan@protonmail.com>
Date: Sun, 27 Mar 2022 08:20:15 +0700
stage2: sparcv9: Add some initial checks in codegen
Diffstat:
1 file changed, 8 insertions(+), 0 deletions(-)
diff --git a/src/arch/sparcv9/CodeGen.zig b/src/arch/sparcv9/CodeGen.zig
@@ -1,6 +1,7 @@
//! SPARCv9 codegen.
//! This lowers AIR into MIR.
const std = @import("std");
+const assert = std.debug.assert;
const builtin = @import("builtin");
const link = @import("../../link.zig");
const Module = @import("../../Module.zig");
@@ -8,6 +9,7 @@ const Air = @import("../../Air.zig");
const Mir = @import("Mir.zig");
const Emit = @import("Emit.zig");
const Liveness = @import("../../Liveness.zig");
+const build_options = @import("build_options");
const GenerateSymbolError = @import("../../codegen.zig").GenerateSymbolError;
const FnResult = @import("../../codegen.zig").FnResult;
@@ -35,5 +37,11 @@ pub fn generate(
_ = code;
_ = debug_output;
+ if (build_options.skip_non_native and builtin.cpu.arch != bin_file.options.target.cpu.arch) {
+ @panic("Attempted to compile for architecture that was disabled by build configuration");
+ }
+
+ assert(module_fn.owner_decl.has_tv);
+
@panic("TODO implement SPARCv9 codegen");
}