zig

commit a5a9ffb90b9427efbad40404a9a830ddb42b88b6 (tree)
parent 081d6d12a14d99e2e5d892df1a8e9697700c4644
Author: Alex Rønne Petersen <alex@alexrp.com>
Date:   Mon,  6 Oct 2025 16:37:40 +0200

std.debug.cpu_context: check for architecture, i.e. register size, not bitness

We care about the hardware here, not the ABI.

Diffstat:
M
lib/std/debug/cpu_context.zig
 | 
16
++++++++++------

1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/lib/std/debug/cpu_context.zig b/lib/std/debug/cpu_context.zig
@@ -581,12 +581,14 @@ pub const Hexagon = extern struct {
 /// This is an `extern struct` so that inline assembly in `current` can use field offsets.
 pub const LoongArch = extern struct {
     /// The numbered general-purpose registers r0 - r31. r0 must be zero.
-    r: [32]usize,
-    pc: usize,
+    r: [32]Gpr,
+    pc: Gpr,
+
+    pub const Gpr = if (builtin.target.cpu.arch == .loongarch64) u64 else u32;
 
     pub inline fn current() LoongArch {
         var ctx: LoongArch = undefined;
-        asm volatile (if (@sizeOf(usize) == 8)
+        asm volatile (if (Gpr == u64)
                 \\ st.d $zero, $t0, 0
                 \\ st.d $ra, $t0, 8
                 \\ st.d $tp, $t0, 16
@@ -679,12 +681,14 @@ pub const LoongArch = extern struct {
 /// This is an `extern struct` so that inline assembly in `current` can use field offsets.
 pub const Riscv = extern struct {
     /// The numbered general-purpose registers r0 - r31. r0 must be zero.
-    r: [32]usize,
-    pc: usize,
+    r: [32]Gpr,
+    pc: Gpr,
+
+    pub const Gpr = if (builtin.target.cpu.arch.isRiscv64()) u64 else u32;
 
     pub inline fn current() Riscv {
         var ctx: Riscv = undefined;
-        asm volatile (if (@sizeOf(usize) == 8)
+        asm volatile (if (Gpr == u64)
                 \\ sd zero, 0(t0)
                 \\ sd ra, 8(t0)
                 \\ sd sp, 16(t0)