zig

commit a9f06d16fd6fe6d0eae2a2a545986fa9e53ef9a8 (tree)
parent d94e061ade545f3fbdd4ab1a18f860b05050ebf6
Author: Luna Schwalbe <dev@luna.gl>
Date:   Thu,  4 Sep 2025 16:15:00 +0200

Reenable std.fmt.test.vector for riscv64

The vector codegen issue as described in
https://github.com/ziglang/zig/issues/4486 has been fixed upstream.

Diffstat:
M
lib/std/fmt.zig
 | 
4
----

1 file changed, 0 insertions(+), 4 deletions(-)
diff --git a/lib/std/fmt.zig b/lib/std/fmt.zig
@@ -1211,10 +1211,6 @@ test "positional/alignment/width/precision" {
 
 test "vector" {
     if ((builtin.cpu.arch == .armeb or builtin.cpu.arch == .thumbeb) and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest; // https://github.com/ziglang/zig/issues/22060
-    if (builtin.target.cpu.arch == .riscv64) {
-        // https://github.com/ziglang/zig/issues/4486
-        return error.SkipZigTest;
-    }
 
     const vbool: @Vector(4, bool) = [_]bool{ true, false, true, false };
     const vi64: @Vector(4, i64) = [_]i64{ -2, -1, 0, 1 };