zig

commit ae10adb6ef7182352c6176a135e181ba70c81212 (tree)
parent a0205fff98f1e3df24d28b78b86d6e8f385d350f
Author: Alex Rønne Petersen <alex@alexrp.com>
Date:   Sat, 31 Aug 2024 03:29:46 +0200

llvm: Don't lower to f16 for riscv32.

This causes so many test failures that I doubt this has been tested at all.

Diffstat:
M
src/codegen/llvm.zig
 | 
1
+

1 file changed, 1 insertion(+), 0 deletions(-)
diff --git a/src/codegen/llvm.zig b/src/codegen/llvm.zig
@@ -11990,6 +11990,7 @@ fn backendSupportsF16(target: std.Target) bool {
         .mipsel,
         .mips64,
         .mips64el,
+        .riscv32,
         .s390x,
         => false,
         .aarch64,