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Switch CPU/features to simple format

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This commit is contained in:
Layne Gustafson
2019-12-20 19:27:13 -05:00
committed by Andrew Kelley
parent 9d66bda264
commit c131e50ea7
51 changed files with 21721 additions and 13386 deletions
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78
lib/std/target.zig
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@@ -2,9 +2,6 @@ const std = @import("std.zig");
const mem = std.mem;
const builtin = std.builtin;
pub const feature = @import("target/feature.zig");
pub const cpu = @import("target/cpu.zig");
/// TODO Nearly all the functions in this namespace would be
/// better off if https://github.com/ziglang/zig/issues/425
/// was solved.
@@ -844,3 +841,78 @@ pub const Target = union(enum) {
return .unavailable;
}
};
pub const aarch64 = @import("target/aarch64.zig");
pub const amdgpu = @import("target/amdgpu.zig");
pub const arm = @import("target/arm.zig");
pub const avr = @import("target/avr.zig");
pub const bpf = @import("target/bpf.zig");
pub const hexagon = @import("target/hexagon.zig");
pub const mips = @import("target/mips.zig");
pub const msp430 = @import("target/msp430.zig");
pub const nvptx = @import("target/nvptx.zig");
pub const powerpc = @import("target/powerpc.zig");
pub const riscv = @import("target/riscv.zig");
pub const sparc = @import("target/sparc.zig");
pub const systemz = @import("target/systemz.zig");
pub const wasm = @import("target/wasm.zig");
pub const x86 = @import("target/x86.zig");
pub const Feature = struct {
name: []const u8,
description: []const u8,
llvm_name: []const u8,
subfeatures: []*const Feature,
};
pub const Cpu = struct {
name: []const u8,
llvm_name: []const u8,
subfeatures: []*const Feature,
};
pub fn getFeaturesForArch(arch: @TagType(Target.Arch)) []*const Feature {
return switch (arch) {
.arm, .armeb, .thumb, .thumbeb => arm.features,
.aarch64, .aarch64_be, .aarch64_32 => aarch64.features,
.avr => avr.features,
.bpfel, .bpfeb => bpf.features,
.hexagon => hexagon.features,
.mips, .mipsel, .mips64, .mips64el => mips.features,
.msp430 => msp430.features,
.powerpc, .powerpc64, .powerpc64le => powerpc.features,
.amdgcn => amdgpu.features,
.riscv32, .riscv64 => riscv.features,
.sparc, .sparcv9, .sparcel => sparc.features,
.s390x => systemz.features,
.i386, .x86_64 => x86.features,
.nvptx, .nvptx64 => nvptx.features,
.wasm32, .wasm64 => wasm.features,
else => &[_]*const Feature{},
};
}
pub fn getCpusForArch(arch: @TagType(Target.Arch)) []*const Cpu {
return switch (arch) {
.arm, .armeb, .thumb, .thumbeb => arm.cpus,
.aarch64, .aarch64_be, .aarch64_32 => aarch64.cpus,
.avr => avr.cpus,
.bpfel, .bpfeb => bpf.cpus,
.hexagon => hexagon.cpus,
.mips, .mipsel, .mips64, .mips64el => mips.cpus,
.msp430 => msp430.cpus,
.powerpc, .powerpc64, .powerpc64le => powerpc.cpus,
.amdgcn => amdgpu.cpus,
.riscv32, .riscv64 => riscv.cpus,
.sparc, .sparcv9, .sparcel => sparc.cpus,
.s390x => systemz.cpus,
.i386, .x86_64 => x86.cpus,
.nvptx, .nvptx64 => nvptx.cpus,
.wasm32, .wasm64 => wasm.cpus,
else => &[_]*const Cpu{},
};
}

2383
lib/std/target/aarch64.zig Normal file
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2329
lib/std/target/amdgpu.zig Normal file
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3595
lib/std/target/arm.zig Normal file
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5578
lib/std/target/avr.zig Normal file
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75
lib/std/target/bpf.zig Normal file
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@@ -0,0 +1,75 @@
const Feature = @import("std").target.Feature;
const Cpu = @import("std").target.Cpu;
pub const feature_alu32 = Feature{
.name = "alu32",
.description = "Enable ALU32 instructions",
.llvm_name = "alu32",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_dummy = Feature{
.name = "dummy",
.description = "unused feature",
.llvm_name = "dummy",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_dwarfris = Feature{
.name = "dwarfris",
.description = "Disable MCAsmInfo DwarfUsesRelocationsAcrossSections",
.llvm_name = "dwarfris",
.subfeatures = &[_]*const Feature {
},
};
pub const features = &[_]*const Feature {
&feature_alu32,
&feature_dummy,
&feature_dwarfris,
};
pub const cpu_generic = Cpu{
.name = "generic",
.llvm_name = "generic",
.subfeatures = &[_]*const Feature {
},
};
pub const cpu_probe = Cpu{
.name = "probe",
.llvm_name = "probe",
.subfeatures = &[_]*const Feature {
},
};
pub const cpu_v1 = Cpu{
.name = "v1",
.llvm_name = "v1",
.subfeatures = &[_]*const Feature {
},
};
pub const cpu_v2 = Cpu{
.name = "v2",
.llvm_name = "v2",
.subfeatures = &[_]*const Feature {
},
};
pub const cpu_v3 = Cpu{
.name = "v3",
.llvm_name = "v3",
.subfeatures = &[_]*const Feature {
},
};
pub const cpus = &[_]*const Cpu {
&cpu_generic,
&cpu_probe,
&cpu_v1,
&cpu_v2,
&cpu_v3,
};

67
lib/std/target/cpu.zig
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@@ -1,67 +0,0 @@
const std = @import("std");
const feature = @import("feature.zig");
const Arch = std.Target.Arch;
pub const AArch64Cpu = @import("cpu/AArch64Cpu.zig").AArch64Cpu;
pub const AmdGpuCpu = @import("cpu/AmdGpuCpu.zig").AmdGpuCpu;
pub const ArmCpu = @import("cpu/ArmCpu.zig").ArmCpu;
pub const AvrCpu = @import("cpu/AvrCpu.zig").AvrCpu;
pub const BpfCpu = @import("cpu/BpfCpu.zig").BpfCpu;
pub const HexagonCpu = @import("cpu/HexagonCpu.zig").HexagonCpu;
pub const MipsCpu = @import("cpu/MipsCpu.zig").MipsCpu;
pub const Msp430Cpu = @import("cpu/Msp430Cpu.zig").Msp430Cpu;
pub const NvptxCpu = @import("cpu/NvptxCpu.zig").NvptxCpu;
pub const PowerPcCpu = @import("cpu/PowerPcCpu.zig").PowerPcCpu;
pub const RiscVCpu = @import("cpu/RiscVCpu.zig").RiscVCpu;
pub const SparcCpu = @import("cpu/SparcCpu.zig").SparcCpu;
pub const SystemZCpu = @import("cpu/SystemZCpu.zig").SystemZCpu;
pub const WebAssemblyCpu = @import("cpu/WebAssemblyCpu.zig").WebAssemblyCpu;
pub const X86Cpu = @import("cpu/X86Cpu.zig").X86Cpu;
pub const EmptyCpu = @import("cpu/empty.zig").EmptyCpu;
pub fn ArchCpu(comptime arch: @TagType(Arch)) type {
return switch (arch) {
.arm, .armeb, .thumb, .thumbeb => ArmCpu,
.aarch64, .aarch64_be, .aarch64_32 => AArch64Cpu,
.avr => AvrCpu,
.bpfel, .bpfeb => BpfCpu,
.hexagon => HexagonCpu,
.mips, .mipsel, .mips64, .mips64el => MipsCpu,
.msp430 => Msp430Cpu,
.powerpc, .powerpc64, .powerpc64le => PowerPcCpu,
.amdgcn => AmdGpuCpu,
.riscv32, .riscv64 => RiscVCpu,
.sparc, .sparcv9, .sparcel => SparcCpu,
.s390x => SystemZCpu,
.i386, .x86_64 => X86Cpu,
.nvptx, .nvptx64 => NvptxCpu,
.wasm32, .wasm64 => WebAssemblyCpu,
else => EmptyCpu,
};
}
pub fn ArchCpuInfo(comptime arch: @TagType(Arch)) type {
return CpuInfo(ArchCpu(arch), feature.ArchFeature(arch));
}
pub fn CpuInfo(comptime CpuType: type, comptime FeatureType: type) type {
return struct {
value: CpuType,
name: []const u8,
features: []const FeatureType,
const Self = @This();
pub fn create(value: CpuType, name: []const u8, features: []const FeatureType) Self {
return Self {
.value = value,
.name = name,
.features = features,
};
}
};
}

480
lib/std/target/cpu/AArch64Cpu.zig
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@@ -1,480 +0,0 @@
const feature = @import("std").target.feature;
const CpuInfo = @import("std").target.cpu.CpuInfo;
pub const AArch64Cpu = enum {
AppleLatest,
CortexA35,
CortexA53,
CortexA55,
CortexA57,
CortexA65,
CortexA65ae,
CortexA72,
CortexA73,
CortexA75,
CortexA76,
CortexA76ae,
Cyclone,
ExynosM1,
ExynosM2,
ExynosM3,
ExynosM4,
ExynosM5,
Falkor,
Generic,
Kryo,
NeoverseE1,
NeoverseN1,
Saphira,
Thunderx,
Thunderx2t99,
Thunderxt81,
Thunderxt83,
Thunderxt88,
Tsv110,
const FeatureType = feature.AArch64Feature;
pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
return cpu_infos[@enumToInt(self)];
}
pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
CpuInfo(@This(), FeatureType).create(.AppleLatest, "apple-latest", &[_]FeatureType {
.ArithBccFusion,
.ArithCbzFusion,
.ZczFp,
.AlternateSextloadCvtF32Pattern,
.DisableLatencySchedHeuristic,
.Perfmon,
.ZczGp,
.ZczFpWorkaround,
.Zcm,
.FpArmv8,
.FuseCryptoEor,
.FuseAes,
.Cyclone,
}),
CpuInfo(@This(), FeatureType).create(.CortexA35, "cortex-a35", &[_]FeatureType {
.Perfmon,
.FpArmv8,
.Crc,
.A35,
}),
CpuInfo(@This(), FeatureType).create(.CortexA53, "cortex-a53", &[_]FeatureType {
.Perfmon,
.UsePostraScheduler,
.Crc,
.CustomCheapAsMove,
.BalanceFpOps,
.UseAa,
.FpArmv8,
.FuseAes,
.A53,
}),
CpuInfo(@This(), FeatureType).create(.CortexA55, "cortex-a55", &[_]FeatureType {
.Lse,
.Vh,
.Rdm,
.Perfmon,
.Pan,
.Dotprod,
.Crc,
.Lor,
.Uaops,
.Ras,
.Rcpc,
.Ccpp,
.FpArmv8,
.FuseAes,
.A55,
}),
CpuInfo(@This(), FeatureType).create(.CortexA57, "cortex-a57", &[_]FeatureType {
.Perfmon,
.UsePostraScheduler,
.Crc,
.PredictableSelectExpensive,
.CustomCheapAsMove,
.BalanceFpOps,
.FuseLiterals,
.FpArmv8,
.FuseAes,
.A57,
}),
CpuInfo(@This(), FeatureType).create(.CortexA65, "cortex-a65", &[_]FeatureType {
.Lse,
.Vh,
.Rdm,
.Pan,
.Dotprod,
.Crc,
.Ssbs,
.Lor,
.Uaops,
.Ras,
.Rcpc,
.Ccpp,
.FpArmv8,
.A65,
}),
CpuInfo(@This(), FeatureType).create(.CortexA65ae, "cortex-a65ae", &[_]FeatureType {
.Lse,
.Vh,
.Rdm,
.Pan,
.Dotprod,
.Crc,
.Ssbs,
.Lor,
.Uaops,
.Ras,
.Rcpc,
.Ccpp,
.FpArmv8,
.A65,
}),
CpuInfo(@This(), FeatureType).create(.CortexA72, "cortex-a72", &[_]FeatureType {
.Perfmon,
.FpArmv8,
.Crc,
.FuseAes,
.A72,
}),
CpuInfo(@This(), FeatureType).create(.CortexA73, "cortex-a73", &[_]FeatureType {
.Perfmon,
.FpArmv8,
.Crc,
.FuseAes,
.A73,
}),
CpuInfo(@This(), FeatureType).create(.CortexA75, "cortex-a75", &[_]FeatureType {
.Lse,
.Vh,
.Rdm,
.Perfmon,
.Pan,
.Dotprod,
.Crc,
.Lor,
.Uaops,
.Ras,
.Rcpc,
.Ccpp,
.FpArmv8,
.FuseAes,
.A75,
}),
CpuInfo(@This(), FeatureType).create(.CortexA76, "cortex-a76", &[_]FeatureType {
.Lse,
.Vh,
.Rdm,
.Pan,
.Dotprod,
.Crc,
.Ssbs,
.Lor,
.Uaops,
.Ras,
.Rcpc,
.Ccpp,
.FpArmv8,
.A76,
}),
CpuInfo(@This(), FeatureType).create(.CortexA76ae, "cortex-a76ae", &[_]FeatureType {
.Lse,
.Vh,
.Rdm,
.Pan,
.Dotprod,
.Crc,
.Ssbs,
.Lor,
.Uaops,
.Ras,
.Rcpc,
.Ccpp,
.FpArmv8,
.A76,
}),
CpuInfo(@This(), FeatureType).create(.Cyclone, "cyclone", &[_]FeatureType {
.ArithBccFusion,
.ArithCbzFusion,
.ZczFp,
.AlternateSextloadCvtF32Pattern,
.DisableLatencySchedHeuristic,
.Perfmon,
.ZczGp,
.ZczFpWorkaround,
.Zcm,
.FpArmv8,
.FuseCryptoEor,
.FuseAes,
.Cyclone,
}),
CpuInfo(@This(), FeatureType).create(.ExynosM1, "exynos-m1", &[_]FeatureType {
.ZczFp,
.Perfmon,
.UsePostraScheduler,
.Crc,
.UseReciprocalSquareRoot,
.CustomCheapAsMove,
.Force32bitJumpTables,
.SlowMisaligned128store,
.FpArmv8,
.SlowPaired128,
.FuseAes,
.Exynosm1,
}),
CpuInfo(@This(), FeatureType).create(.ExynosM2, "exynos-m2", &[_]FeatureType {
.ZczFp,
.Perfmon,
.UsePostraScheduler,
.Crc,
.CustomCheapAsMove,
.Force32bitJumpTables,
.SlowMisaligned128store,
.FpArmv8,
.SlowPaired128,
.FuseAes,
.Exynosm2,
}),
CpuInfo(@This(), FeatureType).create(.ExynosM3, "exynos-m3", &[_]FeatureType {
.FuseCsel,
.ZczFp,
.Perfmon,
.UsePostraScheduler,
.Crc,
.PredictableSelectExpensive,
.CustomCheapAsMove,
.Force32bitJumpTables,
.FuseLiterals,
.FuseAddress,
.LslFast,
.FpArmv8,
.FuseAes,
.Exynosm3,
}),
CpuInfo(@This(), FeatureType).create(.ExynosM4, "exynos-m4", &[_]FeatureType {
.ArithBccFusion,
.Vh,
.ArithCbzFusion,
.ZczFp,
.Rdm,
.UsePostraScheduler,
.Ras,
.Force32bitJumpTables,
.Ccpp,
.FuseCsel,
.Pan,
.Uaops,
.FuseLiterals,
.LslFast,
.Lse,
.Perfmon,
.Dotprod,
.Lor,
.FuseArithLogic,
.Crc,
.CustomCheapAsMove,
.FuseAddress,
.ZczGp,
.FpArmv8,
.FuseAes,
.Exynosm4,
}),
CpuInfo(@This(), FeatureType).create(.ExynosM5, "exynos-m5", &[_]FeatureType {
.ArithBccFusion,
.Vh,
.ArithCbzFusion,
.ZczFp,
.Rdm,
.UsePostraScheduler,
.Ras,
.Force32bitJumpTables,
.Ccpp,
.FuseCsel,
.Pan,
.Uaops,
.FuseLiterals,
.LslFast,
.Lse,
.Perfmon,
.Dotprod,
.Lor,
.FuseArithLogic,
.Crc,
.CustomCheapAsMove,
.FuseAddress,
.ZczGp,
.FpArmv8,
.FuseAes,
.Exynosm4,
}),
CpuInfo(@This(), FeatureType).create(.Falkor, "falkor", &[_]FeatureType {
.ZczFp,
.Rdm,
.Perfmon,
.UsePostraScheduler,
.Crc,
.PredictableSelectExpensive,
.CustomCheapAsMove,
.ZczGp,
.FpArmv8,
.SlowStrqroStore,
.LslFast,
.Falkor,
}),
CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
.Trbe,
.Ete,
.FpArmv8,
.FuseAes,
.Neon,
.Perfmon,
.UsePostraScheduler,
}),
CpuInfo(@This(), FeatureType).create(.Kryo, "kryo", &[_]FeatureType {
.ZczFp,
.Perfmon,
.UsePostraScheduler,
.Crc,
.PredictableSelectExpensive,
.CustomCheapAsMove,
.ZczGp,
.FpArmv8,
.LslFast,
.Kryo,
}),
CpuInfo(@This(), FeatureType).create(.NeoverseE1, "neoverse-e1", &[_]FeatureType {
.Lse,
.Vh,
.Rdm,
.Pan,
.Dotprod,
.Crc,
.Ssbs,
.Lor,
.Uaops,
.Ras,
.Rcpc,
.Ccpp,
.FpArmv8,
.Neoversee1,
}),
CpuInfo(@This(), FeatureType).create(.NeoverseN1, "neoverse-n1", &[_]FeatureType {
.Lse,
.Spe,
.Vh,
.Rdm,
.Pan,
.Dotprod,
.Crc,
.Ssbs,
.Lor,
.Uaops,
.Ras,
.Rcpc,
.Ccpp,
.FpArmv8,
.Neoversen1,
}),
CpuInfo(@This(), FeatureType).create(.Saphira, "saphira", &[_]FeatureType {
.Spe,
.Vh,
.ZczFp,
.Rdm,
.UsePostraScheduler,
.Dit,
.Am,
.Ras,
.Rcpc,
.Sel2,
.Ccpp,
.Pa,
.Pan,
.Uaops,
.Tracev84,
.Mpam,
.LslFast,
.Lse,
.Nv,
.Perfmon,
.Dotprod,
.TlbRmi,
.Lor,
.Ccidx,
.PredictableSelectExpensive,
.Crc,
.CustomCheapAsMove,
.Fmi,
.ZczGp,
.FpArmv8,
.Saphira,
}),
CpuInfo(@This(), FeatureType).create(.Thunderx, "thunderx", &[_]FeatureType {
.Perfmon,
.UsePostraScheduler,
.Crc,
.FpArmv8,
.PredictableSelectExpensive,
.Thunderx,
}),
CpuInfo(@This(), FeatureType).create(.Thunderx2t99, "thunderx2t99", &[_]FeatureType {
.Lse,
.ArithBccFusion,
.Vh,
.Rdm,
.UsePostraScheduler,
.Crc,
.Lor,
.Pan,
.AggressiveFma,
.FpArmv8,
.PredictableSelectExpensive,
.Thunderx2t99,
}),
CpuInfo(@This(), FeatureType).create(.Thunderxt81, "thunderxt81", &[_]FeatureType {
.Perfmon,
.UsePostraScheduler,
.Crc,
.FpArmv8,
.PredictableSelectExpensive,
.Thunderxt81,
}),
CpuInfo(@This(), FeatureType).create(.Thunderxt83, "thunderxt83", &[_]FeatureType {
.Perfmon,
.UsePostraScheduler,
.Crc,
.FpArmv8,
.PredictableSelectExpensive,
.Thunderxt83,
}),
CpuInfo(@This(), FeatureType).create(.Thunderxt88, "thunderxt88", &[_]FeatureType {
.Perfmon,
.UsePostraScheduler,
.Crc,
.FpArmv8,
.PredictableSelectExpensive,
.Thunderxt88,
}),
CpuInfo(@This(), FeatureType).create(.Tsv110, "tsv110", &[_]FeatureType {
.Lse,
.Spe,
.Vh,
.Rdm,
.Perfmon,
.UsePostraScheduler,
.Pan,
.Dotprod,
.Crc,
.Lor,
.Uaops,
.CustomCheapAsMove,
.Ras,
.Ccpp,
.FpArmv8,
.FuseAes,
.Tsv110,
}),
};
};

1060
lib/std/target/cpu/AmdGpuCpu.zig
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lib/std/target/cpu/ArmCpu.zig
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3863
lib/std/target/cpu/AvrCpu.zig
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29
lib/std/target/cpu/BpfCpu.zig
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@@ -1,29 +0,0 @@
const feature = @import("std").target.feature;
const CpuInfo = @import("std").target.cpu.CpuInfo;
pub const BpfCpu = enum {
Generic,
Probe,
V1,
V2,
V3,
const FeatureType = feature.BpfFeature;
pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
return cpu_infos[@enumToInt(self)];
}
pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Probe, "probe", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.V1, "v1", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.V2, "v2", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.V3, "v3", &[_]FeatureType {
}),
};
};

103
lib/std/target/cpu/HexagonCpu.zig
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@@ -1,103 +0,0 @@
const feature = @import("std").target.feature;
const CpuInfo = @import("std").target.cpu.CpuInfo;
pub const HexagonCpu = enum {
Generic,
Hexagonv5,
Hexagonv55,
Hexagonv60,
Hexagonv62,
Hexagonv65,
Hexagonv66,
const FeatureType = feature.HexagonFeature;
pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
return cpu_infos[@enumToInt(self)];
}
pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
.V5,
.V55,
.V60,
.Duplex,
.Memops,
.Packets,
.Nvj,
.Nvs,
.SmallData,
}),
CpuInfo(@This(), FeatureType).create(.Hexagonv5, "hexagonv5", &[_]FeatureType {
.V5,
.Duplex,
.Memops,
.Packets,
.Nvj,
.Nvs,
.SmallData,
}),
CpuInfo(@This(), FeatureType).create(.Hexagonv55, "hexagonv55", &[_]FeatureType {
.V5,
.V55,
.Duplex,
.Memops,
.Packets,
.Nvj,
.Nvs,
.SmallData,
}),
CpuInfo(@This(), FeatureType).create(.Hexagonv60, "hexagonv60", &[_]FeatureType {
.V5,
.V55,
.V60,
.Duplex,
.Memops,
.Packets,
.Nvj,
.Nvs,
.SmallData,
}),
CpuInfo(@This(), FeatureType).create(.Hexagonv62, "hexagonv62", &[_]FeatureType {
.V5,
.V55,
.V60,
.V62,
.Duplex,
.Memops,
.Packets,
.Nvj,
.Nvs,
.SmallData,
}),
CpuInfo(@This(), FeatureType).create(.Hexagonv65, "hexagonv65", &[_]FeatureType {
.V5,
.V55,
.V60,
.V62,
.V65,
.Duplex,
.Mem_noshuf,
.Memops,
.Packets,
.Nvj,
.Nvs,
.SmallData,
}),
CpuInfo(@This(), FeatureType).create(.Hexagonv66, "hexagonv66", &[_]FeatureType {
.V5,
.V55,
.V60,
.V62,
.V65,
.V66,
.Duplex,
.Mem_noshuf,
.Memops,
.Packets,
.Nvj,
.Nvs,
.SmallData,
}),
};
};

190
lib/std/target/cpu/MipsCpu.zig
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@@ -1,190 +0,0 @@
const feature = @import("std").target.feature;
const CpuInfo = @import("std").target.cpu.CpuInfo;
pub const MipsCpu = enum {
Mips1,
Mips2,
Mips3,
Mips32,
Mips32r2,
Mips32r3,
Mips32r5,
Mips32r6,
Mips4,
Mips5,
Mips64,
Mips64r2,
Mips64r3,
Mips64r5,
Mips64r6,
Octeon,
P5600,
const FeatureType = feature.MipsFeature;
pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
return cpu_infos[@enumToInt(self)];
}
pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
CpuInfo(@This(), FeatureType).create(.Mips1, "mips1", &[_]FeatureType {
.Mips1,
}),
CpuInfo(@This(), FeatureType).create(.Mips2, "mips2", &[_]FeatureType {
.Mips1,
.Mips2,
}),
CpuInfo(@This(), FeatureType).create(.Mips3, "mips3", &[_]FeatureType {
.Mips3_32r2,
.Fp64,
.Gp64,
.Mips1,
.Mips3_32,
.Mips3,
}),
CpuInfo(@This(), FeatureType).create(.Mips32, "mips32", &[_]FeatureType {
.Mips4_32,
.Mips1,
.Mips3_32,
.Mips32,
}),
CpuInfo(@This(), FeatureType).create(.Mips32r2, "mips32r2", &[_]FeatureType {
.Mips5_32r2,
.Mips4_32r2,
.Mips3_32r2,
.Mips4_32,
.Mips1,
.Mips3_32,
.Mips32r2,
}),
CpuInfo(@This(), FeatureType).create(.Mips32r3, "mips32r3", &[_]FeatureType {
.Mips5_32r2,
.Mips3_32r2,
.Mips4_32r2,
.Mips4_32,
.Mips1,
.Mips3_32,
.Mips32r3,
}),
CpuInfo(@This(), FeatureType).create(.Mips32r5, "mips32r5", &[_]FeatureType {
.Mips5_32r2,
.Mips3_32r2,
.Mips4_32r2,
.Mips4_32,
.Mips1,
.Mips3_32,
.Mips32r5,
}),
CpuInfo(@This(), FeatureType).create(.Mips32r6, "mips32r6", &[_]FeatureType {
.Mips5_32r2,
.Mips3_32r2,
.Mips4_32r2,
.Abs2008,
.Nan2008,
.Fp64,
.Mips4_32,
.Mips1,
.Mips3_32,
.Mips32r6,
}),
CpuInfo(@This(), FeatureType).create(.Mips4, "mips4", &[_]FeatureType {
.Mips3_32r2,
.Mips4_32r2,
.Fp64,
.Gp64,
.Mips4_32,
.Mips1,
.Mips3_32,
.Mips4,
}),
CpuInfo(@This(), FeatureType).create(.Mips5, "mips5", &[_]FeatureType {
.Mips5_32r2,
.Mips4_32r2,
.Mips3_32r2,
.Gp64,
.Fp64,
.Mips4_32,
.Mips1,
.Mips3_32,
.Mips5,
}),
CpuInfo(@This(), FeatureType).create(.Mips64, "mips64", &[_]FeatureType {
.Mips5_32r2,
.Mips3_32r2,
.Mips4_32r2,
.Gp64,
.Fp64,
.Mips4_32,
.Mips1,
.Mips3_32,
.Mips64,
}),
CpuInfo(@This(), FeatureType).create(.Mips64r2, "mips64r2", &[_]FeatureType {
.Mips5_32r2,
.Mips3_32r2,
.Mips4_32r2,
.Gp64,
.Fp64,
.Mips4_32,
.Mips1,
.Mips3_32,
.Mips64r2,
}),
CpuInfo(@This(), FeatureType).create(.Mips64r3, "mips64r3", &[_]FeatureType {
.Mips5_32r2,
.Mips3_32r2,
.Mips4_32r2,
.Gp64,
.Fp64,
.Mips4_32,
.Mips1,
.Mips3_32,
.Mips64r3,
}),
CpuInfo(@This(), FeatureType).create(.Mips64r5, "mips64r5", &[_]FeatureType {
.Mips5_32r2,
.Mips3_32r2,
.Mips4_32r2,
.Gp64,
.Fp64,
.Mips4_32,
.Mips1,
.Mips3_32,
.Mips64r5,
}),
CpuInfo(@This(), FeatureType).create(.Mips64r6, "mips64r6", &[_]FeatureType {
.Mips5_32r2,
.Mips3_32r2,
.Nan2008,
.Abs2008,
.Mips4_32r2,
.Fp64,
.Gp64,
.Mips4_32,
.Mips1,
.Mips3_32,
.Mips64r6,
}),
CpuInfo(@This(), FeatureType).create(.Octeon, "octeon", &[_]FeatureType {
.Mips5_32r2,
.Mips3_32r2,
.Mips4_32r2,
.Gp64,
.Fp64,
.Mips4_32,
.Mips1,
.Mips3_32,
.Cnmips,
.Mips64r2,
}),
CpuInfo(@This(), FeatureType).create(.P5600, "p5600", &[_]FeatureType {
.Mips5_32r2,
.Mips3_32r2,
.Mips4_32r2,
.Mips4_32,
.Mips1,
.Mips3_32,
.P5600,
}),
};
};

24
lib/std/target/cpu/Msp430Cpu.zig
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@@ -1,24 +0,0 @@
const feature = @import("std").target.feature;
const CpuInfo = @import("std").target.cpu.CpuInfo;
pub const Msp430Cpu = enum {
Generic,
Msp430,
Msp430x,
const FeatureType = feature.Msp430Feature;
pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
return cpu_infos[@enumToInt(self)];
}
pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Msp430, "msp430", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Msp430x, "msp430x", &[_]FeatureType {
.Ext,
}),
};
};

85
lib/std/target/cpu/NvptxCpu.zig
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@@ -1,85 +0,0 @@
const feature = @import("std").target.feature;
const CpuInfo = @import("std").target.cpu.CpuInfo;
pub const NvptxCpu = enum {
Sm_20,
Sm_21,
Sm_30,
Sm_32,
Sm_35,
Sm_37,
Sm_50,
Sm_52,
Sm_53,
Sm_60,
Sm_61,
Sm_62,
Sm_70,
Sm_72,
Sm_75,
const FeatureType = feature.NvptxFeature;
pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
return cpu_infos[@enumToInt(self)];
}
pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
CpuInfo(@This(), FeatureType).create(.Sm_20, "sm_20", &[_]FeatureType {
.Sm_20,
}),
CpuInfo(@This(), FeatureType).create(.Sm_21, "sm_21", &[_]FeatureType {
.Sm_21,
}),
CpuInfo(@This(), FeatureType).create(.Sm_30, "sm_30", &[_]FeatureType {
.Sm_30,
}),
CpuInfo(@This(), FeatureType).create(.Sm_32, "sm_32", &[_]FeatureType {
.Ptx40,
.Sm_32,
}),
CpuInfo(@This(), FeatureType).create(.Sm_35, "sm_35", &[_]FeatureType {
.Sm_35,
}),
CpuInfo(@This(), FeatureType).create(.Sm_37, "sm_37", &[_]FeatureType {
.Ptx41,
.Sm_37,
}),
CpuInfo(@This(), FeatureType).create(.Sm_50, "sm_50", &[_]FeatureType {
.Ptx40,
.Sm_50,
}),
CpuInfo(@This(), FeatureType).create(.Sm_52, "sm_52", &[_]FeatureType {
.Ptx41,
.Sm_52,
}),
CpuInfo(@This(), FeatureType).create(.Sm_53, "sm_53", &[_]FeatureType {
.Ptx42,
.Sm_53,
}),
CpuInfo(@This(), FeatureType).create(.Sm_60, "sm_60", &[_]FeatureType {
.Ptx50,
.Sm_60,
}),
CpuInfo(@This(), FeatureType).create(.Sm_61, "sm_61", &[_]FeatureType {
.Ptx50,
.Sm_61,
}),
CpuInfo(@This(), FeatureType).create(.Sm_62, "sm_62", &[_]FeatureType {
.Ptx50,
.Sm_62,
}),
CpuInfo(@This(), FeatureType).create(.Sm_70, "sm_70", &[_]FeatureType {
.Ptx60,
.Sm_70,
}),
CpuInfo(@This(), FeatureType).create(.Sm_72, "sm_72", &[_]FeatureType {
.Ptx61,
.Sm_72,
}),
CpuInfo(@This(), FeatureType).create(.Sm_75, "sm_75", &[_]FeatureType {
.Ptx63,
.Sm_75,
}),
};
};

451
lib/std/target/cpu/PowerPcCpu.zig
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@@ -1,451 +0,0 @@
const feature = @import("std").target.feature;
const CpuInfo = @import("std").target.cpu.CpuInfo;
pub const PowerPcCpu = enum {
Cpu440,
Cpu450,
Cpu601,
Cpu602,
Cpu603,
E603,
Ev603,
Cpu604,
E604,
Cpu620,
Cpu7400,
Cpu7450,
Cpu750,
Cpu970,
A2,
A2q,
E500,
E500mc,
E5500,
G3,
G4,
G4plus,
G5,
Generic,
Ppc,
Ppc32,
Ppc64,
Ppc64le,
Pwr3,
Pwr4,
Pwr5,
Pwr5x,
Pwr6,
Pwr6x,
Pwr7,
Pwr8,
Pwr9,
const FeatureType = feature.PowerPcFeature;
pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
return cpu_infos[@enumToInt(self)];
}
pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
CpuInfo(@This(), FeatureType).create(.Cpu440, "440", &[_]FeatureType {
.Icbt,
.Booke,
.HardFloat,
.Fres,
.Frsqrte,
.Isel,
.Msync,
}),
CpuInfo(@This(), FeatureType).create(.Cpu450, "450", &[_]FeatureType {
.Icbt,
.Booke,
.HardFloat,
.Fres,
.Frsqrte,
.Isel,
.Msync,
}),
CpuInfo(@This(), FeatureType).create(.Cpu601, "601", &[_]FeatureType {
.HardFloat,
.Fpu,
}),
CpuInfo(@This(), FeatureType).create(.Cpu602, "602", &[_]FeatureType {
.HardFloat,
.Fpu,
}),
CpuInfo(@This(), FeatureType).create(.Cpu603, "603", &[_]FeatureType {
.HardFloat,
.Fres,
.Frsqrte,
}),
CpuInfo(@This(), FeatureType).create(.E603, "603e", &[_]FeatureType {
.HardFloat,
.Fres,
.Frsqrte,
}),
CpuInfo(@This(), FeatureType).create(.Ev603, "603ev", &[_]FeatureType {
.HardFloat,
.Fres,
.Frsqrte,
}),
CpuInfo(@This(), FeatureType).create(.Cpu604, "604", &[_]FeatureType {
.HardFloat,
.Fres,
.Frsqrte,
}),
CpuInfo(@This(), FeatureType).create(.E604, "604e", &[_]FeatureType {
.HardFloat,
.Fres,
.Frsqrte,
}),
CpuInfo(@This(), FeatureType).create(.Cpu620, "620", &[_]FeatureType {
.HardFloat,
.Fres,
.Frsqrte,
}),
CpuInfo(@This(), FeatureType).create(.Cpu7400, "7400", &[_]FeatureType {
.HardFloat,
.Altivec,
.Fres,
.Frsqrte,
}),
CpuInfo(@This(), FeatureType).create(.Cpu7450, "7450", &[_]FeatureType {
.HardFloat,
.Altivec,
.Fres,
.Frsqrte,
}),
CpuInfo(@This(), FeatureType).create(.Cpu750, "750", &[_]FeatureType {
.HardFloat,
.Fres,
.Frsqrte,
}),
CpuInfo(@This(), FeatureType).create(.Cpu970, "970", &[_]FeatureType {
.Bit64,
.HardFloat,
.Altivec,
.Fres,
.Frsqrte,
.Fsqrt,
.Mfocrf,
.Stfiwx,
}),
CpuInfo(@This(), FeatureType).create(.A2, "a2", &[_]FeatureType {
.Bit64,
.Icbt,
.Booke,
.Cmpb,
.HardFloat,
.Fcpsgn,
.Fpcvt,
.Fprnd,
.Fre,
.Fres,
.Frsqrte,
.Frsqrtes,
.Fsqrt,
.Isel,
.Ldbrx,
.Lfiwax,
.Mfocrf,
.Recipprec,
.Stfiwx,
.SlowPopcntd,
}),
CpuInfo(@This(), FeatureType).create(.A2q, "a2q", &[_]FeatureType {
.Bit64,
.Icbt,
.Booke,
.Cmpb,
.HardFloat,
.Fcpsgn,
.Fpcvt,
.Fprnd,
.Fre,
.Fres,
.Frsqrte,
.Frsqrtes,
.Fsqrt,
.Isel,
.Ldbrx,
.Lfiwax,
.Mfocrf,
.Qpx,
.Recipprec,
.Stfiwx,
.SlowPopcntd,
}),
CpuInfo(@This(), FeatureType).create(.E500, "e500", &[_]FeatureType {
.Icbt,
.Booke,
.Isel,
}),
CpuInfo(@This(), FeatureType).create(.E500mc, "e500mc", &[_]FeatureType {
.Icbt,
.Booke,
.Isel,
.HardFloat,
.Stfiwx,
}),
CpuInfo(@This(), FeatureType).create(.E5500, "e5500", &[_]FeatureType {
.Bit64,
.Icbt,
.Booke,
.Isel,
.Mfocrf,
.HardFloat,
.Stfiwx,
}),
CpuInfo(@This(), FeatureType).create(.G3, "g3", &[_]FeatureType {
.HardFloat,
.Fres,
.Frsqrte,
}),
CpuInfo(@This(), FeatureType).create(.G4, "g4", &[_]FeatureType {
.HardFloat,
.Altivec,
.Fres,
.Frsqrte,
}),
CpuInfo(@This(), FeatureType).create(.G4plus, "g4+", &[_]FeatureType {
.HardFloat,
.Altivec,
.Fres,
.Frsqrte,
}),
CpuInfo(@This(), FeatureType).create(.G5, "g5", &[_]FeatureType {
.Bit64,
.HardFloat,
.Altivec,
.Fres,
.Frsqrte,
.Fsqrt,
.Mfocrf,
.Stfiwx,
}),
CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
.HardFloat,
}),
CpuInfo(@This(), FeatureType).create(.Ppc, "ppc", &[_]FeatureType {
.HardFloat,
}),
CpuInfo(@This(), FeatureType).create(.Ppc32, "ppc32", &[_]FeatureType {
.HardFloat,
}),
CpuInfo(@This(), FeatureType).create(.Ppc64, "ppc64", &[_]FeatureType {
.Bit64,
.HardFloat,
.Altivec,
.Fres,
.Frsqrte,
.Fsqrt,
.Mfocrf,
.Stfiwx,
}),
CpuInfo(@This(), FeatureType).create(.Ppc64le, "ppc64le", &[_]FeatureType {
.Bit64,
.HardFloat,
.Altivec,
.Bpermd,
.Cmpb,
.DirectMove,
.Extdiv,
.Fcpsgn,
.Fpcvt,
.Fprnd,
.Fre,
.Fres,
.Frsqrte,
.Frsqrtes,
.Fsqrt,
.Htm,
.Icbt,
.Isel,
.Ldbrx,
.Lfiwax,
.Mfocrf,
.Power8Altivec,
.Crypto,
.Power8Vector,
.Popcntd,
.PartwordAtomics,
.Recipprec,
.Stfiwx,
.TwoConstNr,
.Vsx,
}),
CpuInfo(@This(), FeatureType).create(.Pwr3, "pwr3", &[_]FeatureType {
.Bit64,
.HardFloat,
.Altivec,
.Fres,
.Frsqrte,
.Mfocrf,
.Stfiwx,
}),
CpuInfo(@This(), FeatureType).create(.Pwr4, "pwr4", &[_]FeatureType {
.Bit64,
.HardFloat,
.Altivec,
.Fres,
.Frsqrte,
.Fsqrt,
.Mfocrf,
.Stfiwx,
}),
CpuInfo(@This(), FeatureType).create(.Pwr5, "pwr5", &[_]FeatureType {
.Bit64,
.HardFloat,
.Altivec,
.Fre,
.Fres,
.Frsqrte,
.Frsqrtes,
.Fsqrt,
.Mfocrf,
.Stfiwx,
}),
CpuInfo(@This(), FeatureType).create(.Pwr5x, "pwr5x", &[_]FeatureType {
.Bit64,
.HardFloat,
.Altivec,
.Fprnd,
.Fre,
.Fres,
.Frsqrte,
.Frsqrtes,
.Fsqrt,
.Mfocrf,
.Stfiwx,
}),
CpuInfo(@This(), FeatureType).create(.Pwr6, "pwr6", &[_]FeatureType {
.Bit64,
.HardFloat,
.Altivec,
.Cmpb,
.Fcpsgn,
.Fprnd,
.Fre,
.Fres,
.Frsqrte,
.Frsqrtes,
.Fsqrt,
.Lfiwax,
.Mfocrf,
.Recipprec,
.Stfiwx,
}),
CpuInfo(@This(), FeatureType).create(.Pwr6x, "pwr6x", &[_]FeatureType {
.Bit64,
.HardFloat,
.Altivec,
.Cmpb,
.Fcpsgn,
.Fprnd,
.Fre,
.Fres,
.Frsqrte,
.Frsqrtes,
.Fsqrt,
.Lfiwax,
.Mfocrf,
.Recipprec,
.Stfiwx,
}),
CpuInfo(@This(), FeatureType).create(.Pwr7, "pwr7", &[_]FeatureType {
.Bit64,
.HardFloat,
.Altivec,
.Bpermd,
.Cmpb,
.Extdiv,
.Fcpsgn,
.Fpcvt,
.Fprnd,
.Fre,
.Fres,
.Frsqrte,
.Frsqrtes,
.Fsqrt,
.Isel,
.Ldbrx,
.Lfiwax,
.Mfocrf,
.Popcntd,
.Recipprec,
.Stfiwx,
.TwoConstNr,
.Vsx,
}),
CpuInfo(@This(), FeatureType).create(.Pwr8, "pwr8", &[_]FeatureType {
.Bit64,
.HardFloat,
.Altivec,
.Bpermd,
.Cmpb,
.DirectMove,
.Extdiv,
.Fcpsgn,
.Fpcvt,
.Fprnd,
.Fre,
.Fres,
.Frsqrte,
.Frsqrtes,
.Fsqrt,
.Htm,
.Icbt,
.Isel,
.Ldbrx,
.Lfiwax,
.Mfocrf,
.Power8Altivec,
.Crypto,
.Power8Vector,
.Popcntd,
.PartwordAtomics,
.Recipprec,
.Stfiwx,
.TwoConstNr,
.Vsx,
}),
CpuInfo(@This(), FeatureType).create(.Pwr9, "pwr9", &[_]FeatureType {
.Bit64,
.HardFloat,
.Altivec,
.Bpermd,
.Cmpb,
.DirectMove,
.Extdiv,
.Fcpsgn,
.Fpcvt,
.Fprnd,
.Fre,
.Fres,
.Frsqrte,
.Frsqrtes,
.Fsqrt,
.Htm,
.Icbt,
.IsaV30Instructions,
.Isel,
.Ldbrx,
.Lfiwax,
.Mfocrf,
.Power8Altivec,
.Crypto,
.Power8Vector,
.Power9Altivec,
.Power9Vector,
.Popcntd,
.PpcPostraSched,
.PpcPreraSched,
.PartwordAtomics,
.Recipprec,
.Stfiwx,
.TwoConstNr,
.Vsx,
.VectorsUseTwoUnits,
}),
};
};

23
lib/std/target/cpu/RiscVCpu.zig
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@@ -1,23 +0,0 @@
const feature = @import("std").target.feature;
const CpuInfo = @import("std").target.cpu.CpuInfo;
pub const RiscVCpu = enum {
GenericRv32,
GenericRv64,
const FeatureType = feature.RiscVFeature;
pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
return cpu_infos[@enumToInt(self)];
}
pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
CpuInfo(@This(), FeatureType).create(.GenericRv32, "generic-rv32", &[_]FeatureType {
.RvcHints,
}),
CpuInfo(@This(), FeatureType).create(.GenericRv64, "generic-rv64", &[_]FeatureType {
.Bit64,
.RvcHints,
}),
};
};

216
lib/std/target/cpu/SparcCpu.zig
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@@ -1,216 +0,0 @@
const feature = @import("std").target.feature;
const CpuInfo = @import("std").target.cpu.CpuInfo;
pub const SparcCpu = enum {
At697e,
At697f,
F934,
Generic,
Gr712rc,
Gr740,
Hypersparc,
Leon2,
Leon3,
Leon4,
Ma2080,
Ma2085,
Ma2100,
Ma2150,
Ma2155,
Ma2450,
Ma2455,
Ma2480,
Ma2485,
Ma2x5x,
Ma2x8x,
Myriad2,
Myriad21,
Myriad22,
Myriad23,
Niagara,
Niagara2,
Niagara3,
Niagara4,
Sparclet,
Sparclite,
Sparclite86x,
Supersparc,
Tsc701,
Ultrasparc,
Ultrasparc3,
Ut699,
V7,
V8,
V9,
const FeatureType = feature.SparcFeature;
pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
return cpu_infos[@enumToInt(self)];
}
pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
CpuInfo(@This(), FeatureType).create(.At697e, "at697e", &[_]FeatureType {
.Leon,
.Insertnopload,
}),
CpuInfo(@This(), FeatureType).create(.At697f, "at697f", &[_]FeatureType {
.Leon,
.Insertnopload,
}),
CpuInfo(@This(), FeatureType).create(.F934, "f934", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Gr712rc, "gr712rc", &[_]FeatureType {
.Leon,
.Hasleoncasa,
}),
CpuInfo(@This(), FeatureType).create(.Gr740, "gr740", &[_]FeatureType {
.Leon,
.Leonpwrpsr,
.Hasleoncasa,
.Leoncyclecounter,
.Hasumacsmac,
}),
CpuInfo(@This(), FeatureType).create(.Hypersparc, "hypersparc", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Leon2, "leon2", &[_]FeatureType {
.Leon,
}),
CpuInfo(@This(), FeatureType).create(.Leon3, "leon3", &[_]FeatureType {
.Leon,
.Hasumacsmac,
}),
CpuInfo(@This(), FeatureType).create(.Leon4, "leon4", &[_]FeatureType {
.Leon,
.Hasleoncasa,
.Hasumacsmac,
}),
CpuInfo(@This(), FeatureType).create(.Ma2080, "ma2080", &[_]FeatureType {
.Leon,
.Hasleoncasa,
}),
CpuInfo(@This(), FeatureType).create(.Ma2085, "ma2085", &[_]FeatureType {
.Leon,
.Hasleoncasa,
}),
CpuInfo(@This(), FeatureType).create(.Ma2100, "ma2100", &[_]FeatureType {
.Leon,
.Hasleoncasa,
}),
CpuInfo(@This(), FeatureType).create(.Ma2150, "ma2150", &[_]FeatureType {
.Leon,
.Hasleoncasa,
}),
CpuInfo(@This(), FeatureType).create(.Ma2155, "ma2155", &[_]FeatureType {
.Leon,
.Hasleoncasa,
}),
CpuInfo(@This(), FeatureType).create(.Ma2450, "ma2450", &[_]FeatureType {
.Leon,
.Hasleoncasa,
}),
CpuInfo(@This(), FeatureType).create(.Ma2455, "ma2455", &[_]FeatureType {
.Leon,
.Hasleoncasa,
}),
CpuInfo(@This(), FeatureType).create(.Ma2480, "ma2480", &[_]FeatureType {
.Leon,
.Hasleoncasa,
}),
CpuInfo(@This(), FeatureType).create(.Ma2485, "ma2485", &[_]FeatureType {
.Leon,
.Hasleoncasa,
}),
CpuInfo(@This(), FeatureType).create(.Ma2x5x, "ma2x5x", &[_]FeatureType {
.Leon,
.Hasleoncasa,
}),
CpuInfo(@This(), FeatureType).create(.Ma2x8x, "ma2x8x", &[_]FeatureType {
.Leon,
.Hasleoncasa,
}),
CpuInfo(@This(), FeatureType).create(.Myriad2, "myriad2", &[_]FeatureType {
.Leon,
.Hasleoncasa,
}),
CpuInfo(@This(), FeatureType).create(.Myriad21, "myriad2.1", &[_]FeatureType {
.Leon,
.Hasleoncasa,
}),
CpuInfo(@This(), FeatureType).create(.Myriad22, "myriad2.2", &[_]FeatureType {
.Leon,
.Hasleoncasa,
}),
CpuInfo(@This(), FeatureType).create(.Myriad23, "myriad2.3", &[_]FeatureType {
.Leon,
.Hasleoncasa,
}),
CpuInfo(@This(), FeatureType).create(.Niagara, "niagara", &[_]FeatureType {
.DeprecatedV8,
.V9,
.Vis,
.Vis2,
}),
CpuInfo(@This(), FeatureType).create(.Niagara2, "niagara2", &[_]FeatureType {
.DeprecatedV8,
.V9,
.Vis,
.Vis2,
.Popc,
}),
CpuInfo(@This(), FeatureType).create(.Niagara3, "niagara3", &[_]FeatureType {
.DeprecatedV8,
.V9,
.Vis,
.Vis2,
.Popc,
}),
CpuInfo(@This(), FeatureType).create(.Niagara4, "niagara4", &[_]FeatureType {
.DeprecatedV8,
.V9,
.Vis,
.Vis2,
.Vis3,
.Popc,
}),
CpuInfo(@This(), FeatureType).create(.Sparclet, "sparclet", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Sparclite, "sparclite", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Sparclite86x, "sparclite86x", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Supersparc, "supersparc", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Tsc701, "tsc701", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Ultrasparc, "ultrasparc", &[_]FeatureType {
.DeprecatedV8,
.V9,
.Vis,
}),
CpuInfo(@This(), FeatureType).create(.Ultrasparc3, "ultrasparc3", &[_]FeatureType {
.DeprecatedV8,
.V9,
.Vis,
.Vis2,
}),
CpuInfo(@This(), FeatureType).create(.Ut699, "ut699", &[_]FeatureType {
.Leon,
.NoFmuls,
.NoFsmuld,
.Fixallfdivsqrt,
.Insertnopload,
}),
CpuInfo(@This(), FeatureType).create(.V7, "v7", &[_]FeatureType {
.NoFsmuld,
.SoftMulDiv,
}),
CpuInfo(@This(), FeatureType).create(.V8, "v8", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.V9, "v9", &[_]FeatureType {
.V9,
}),
};
};

279
lib/std/target/cpu/SystemZCpu.zig
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@@ -1,279 +0,0 @@
const feature = @import("std").target.feature;
const CpuInfo = @import("std").target.cpu.CpuInfo;
pub const SystemZCpu = enum {
Arch10,
Arch11,
Arch12,
Arch13,
Arch8,
Arch9,
Generic,
Z10,
Z13,
Z14,
Z15,
Z196,
ZEC12,
const FeatureType = feature.SystemZFeature;
pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
return cpu_infos[@enumToInt(self)];
}
pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
CpuInfo(@This(), FeatureType).create(.Arch10, "arch10", &[_]FeatureType {
.DfpZonedConversion,
.DistinctOps,
.EnhancedDat2,
.ExecutionHint,
.FpExtension,
.FastSerialization,
.HighWord,
.InterlockedAccess1,
.LoadAndTrap,
.LoadStoreOnCond,
.MessageSecurityAssistExtension3,
.MessageSecurityAssistExtension4,
.MiscellaneousExtensions,
.PopulationCount,
.ProcessorAssist,
.ResetReferenceBitsMultiple,
.TransactionalExecution,
}),
CpuInfo(@This(), FeatureType).create(.Arch11, "arch11", &[_]FeatureType {
.DfpPackedConversion,
.DfpZonedConversion,
.DistinctOps,
.EnhancedDat2,
.ExecutionHint,
.FpExtension,
.FastSerialization,
.HighWord,
.InterlockedAccess1,
.LoadAndTrap,
.LoadAndZeroRightmostByte,
.LoadStoreOnCond,
.LoadStoreOnCond2,
.MessageSecurityAssistExtension3,
.MessageSecurityAssistExtension4,
.MessageSecurityAssistExtension5,
.MiscellaneousExtensions,
.PopulationCount,
.ProcessorAssist,
.ResetReferenceBitsMultiple,
.TransactionalExecution,
.Vector,
}),
CpuInfo(@This(), FeatureType).create(.Arch12, "arch12", &[_]FeatureType {
.DfpPackedConversion,
.DfpZonedConversion,
.DistinctOps,
.EnhancedDat2,
.ExecutionHint,
.FpExtension,
.FastSerialization,
.GuardedStorage,
.HighWord,
.InsertReferenceBitsMultiple,
.InterlockedAccess1,
.LoadAndTrap,
.LoadAndZeroRightmostByte,
.LoadStoreOnCond,
.LoadStoreOnCond2,
.MessageSecurityAssistExtension3,
.MessageSecurityAssistExtension4,
.MessageSecurityAssistExtension5,
.MessageSecurityAssistExtension7,
.MessageSecurityAssistExtension8,
.MiscellaneousExtensions,
.MiscellaneousExtensions2,
.PopulationCount,
.ProcessorAssist,
.ResetReferenceBitsMultiple,
.TransactionalExecution,
.Vector,
.VectorEnhancements1,
.VectorPackedDecimal,
}),
CpuInfo(@This(), FeatureType).create(.Arch13, "arch13", &[_]FeatureType {
.DfpPackedConversion,
.DfpZonedConversion,
.DeflateConversion,
.DistinctOps,
.EnhancedDat2,
.EnhancedSort,
.ExecutionHint,
.FpExtension,
.FastSerialization,
.GuardedStorage,
.HighWord,
.InsertReferenceBitsMultiple,
.InterlockedAccess1,
.LoadAndTrap,
.LoadAndZeroRightmostByte,
.LoadStoreOnCond,
.LoadStoreOnCond2,
.MessageSecurityAssistExtension3,
.MessageSecurityAssistExtension4,
.MessageSecurityAssistExtension5,
.MessageSecurityAssistExtension7,
.MessageSecurityAssistExtension8,
.MessageSecurityAssistExtension9,
.MiscellaneousExtensions,
.MiscellaneousExtensions2,
.MiscellaneousExtensions3,
.PopulationCount,
.ProcessorAssist,
.ResetReferenceBitsMultiple,
.TransactionalExecution,
.Vector,
.VectorEnhancements1,
.VectorEnhancements2,
.VectorPackedDecimal,
.VectorPackedDecimalEnhancement,
}),
CpuInfo(@This(), FeatureType).create(.Arch8, "arch8", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Arch9, "arch9", &[_]FeatureType {
.DistinctOps,
.FpExtension,
.FastSerialization,
.HighWord,
.InterlockedAccess1,
.LoadStoreOnCond,
.MessageSecurityAssistExtension3,
.MessageSecurityAssistExtension4,
.PopulationCount,
.ResetReferenceBitsMultiple,
}),
CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Z10, "z10", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Z13, "z13", &[_]FeatureType {
.DfpPackedConversion,
.DfpZonedConversion,
.DistinctOps,
.EnhancedDat2,
.ExecutionHint,
.FpExtension,
.FastSerialization,
.HighWord,
.InterlockedAccess1,
.LoadAndTrap,
.LoadAndZeroRightmostByte,
.LoadStoreOnCond,
.LoadStoreOnCond2,
.MessageSecurityAssistExtension3,
.MessageSecurityAssistExtension4,
.MessageSecurityAssistExtension5,
.MiscellaneousExtensions,
.PopulationCount,
.ProcessorAssist,
.ResetReferenceBitsMultiple,
.TransactionalExecution,
.Vector,
}),
CpuInfo(@This(), FeatureType).create(.Z14, "z14", &[_]FeatureType {
.DfpPackedConversion,
.DfpZonedConversion,
.DistinctOps,
.EnhancedDat2,
.ExecutionHint,
.FpExtension,
.FastSerialization,
.GuardedStorage,
.HighWord,
.InsertReferenceBitsMultiple,
.InterlockedAccess1,
.LoadAndTrap,
.LoadAndZeroRightmostByte,
.LoadStoreOnCond,
.LoadStoreOnCond2,
.MessageSecurityAssistExtension3,
.MessageSecurityAssistExtension4,
.MessageSecurityAssistExtension5,
.MessageSecurityAssistExtension7,
.MessageSecurityAssistExtension8,
.MiscellaneousExtensions,
.MiscellaneousExtensions2,
.PopulationCount,
.ProcessorAssist,
.ResetReferenceBitsMultiple,
.TransactionalExecution,
.Vector,
.VectorEnhancements1,
.VectorPackedDecimal,
}),
CpuInfo(@This(), FeatureType).create(.Z15, "z15", &[_]FeatureType {
.DfpPackedConversion,
.DfpZonedConversion,
.DeflateConversion,
.DistinctOps,
.EnhancedDat2,
.EnhancedSort,
.ExecutionHint,
.FpExtension,
.FastSerialization,
.GuardedStorage,
.HighWord,
.InsertReferenceBitsMultiple,
.InterlockedAccess1,
.LoadAndTrap,
.LoadAndZeroRightmostByte,
.LoadStoreOnCond,
.LoadStoreOnCond2,
.MessageSecurityAssistExtension3,
.MessageSecurityAssistExtension4,
.MessageSecurityAssistExtension5,
.MessageSecurityAssistExtension7,
.MessageSecurityAssistExtension8,
.MessageSecurityAssistExtension9,
.MiscellaneousExtensions,
.MiscellaneousExtensions2,
.MiscellaneousExtensions3,
.PopulationCount,
.ProcessorAssist,
.ResetReferenceBitsMultiple,
.TransactionalExecution,
.Vector,
.VectorEnhancements1,
.VectorEnhancements2,
.VectorPackedDecimal,
.VectorPackedDecimalEnhancement,
}),
CpuInfo(@This(), FeatureType).create(.Z196, "z196", &[_]FeatureType {
.DistinctOps,
.FpExtension,
.FastSerialization,
.HighWord,
.InterlockedAccess1,
.LoadStoreOnCond,
.MessageSecurityAssistExtension3,
.MessageSecurityAssistExtension4,
.PopulationCount,
.ResetReferenceBitsMultiple,
}),
CpuInfo(@This(), FeatureType).create(.ZEC12, "zEC12", &[_]FeatureType {
.DfpZonedConversion,
.DistinctOps,
.EnhancedDat2,
.ExecutionHint,
.FpExtension,
.FastSerialization,
.HighWord,
.InterlockedAccess1,
.LoadAndTrap,
.LoadStoreOnCond,
.MessageSecurityAssistExtension3,
.MessageSecurityAssistExtension4,
.MiscellaneousExtensions,
.PopulationCount,
.ProcessorAssist,
.ResetReferenceBitsMultiple,
.TransactionalExecution,
}),
};
};

28
lib/std/target/cpu/WebAssemblyCpu.zig
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@@ -1,28 +0,0 @@
const feature = @import("std").target.feature;
const CpuInfo = @import("std").target.cpu.CpuInfo;
pub const WebAssemblyCpu = enum {
BleedingEdge,
Generic,
Mvp,
const FeatureType = feature.WebAssemblyFeature;
pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
return cpu_infos[@enumToInt(self)];
}
pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
CpuInfo(@This(), FeatureType).create(.BleedingEdge, "bleeding-edge", &[_]FeatureType {
.Atomics,
.MutableGlobals,
.NontrappingFptoint,
.Simd128,
.SignExt,
}),
CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Mvp, "mvp", &[_]FeatureType {
}),
};
};

1864
lib/std/target/cpu/X86Cpu.zig
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File diff suppressed because it is too large Load Diff

6
lib/std/target/cpu/empty.zig
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@@ -1,6 +0,0 @@
const feature = @import("std").target.feature;
const CpuInfo = @import("std").target.cpu.CpuInfo;
pub const EmptyCpu = struct {
pub const cpu_infos = [0]CpuInfo(@This(), feature.EmptyFeature) {};
};

81
lib/std/target/feature.zig
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@@ -1,81 +0,0 @@
const builtin = @import("builtin");
const std = @import("std");
const Arch = std.Target.Arch;
pub const AArch64Feature = @import("feature/AArch64Feature.zig").AArch64Feature;
pub const AmdGpuFeature = @import("feature/AmdGpuFeature.zig").AmdGpuFeature;
pub const ArmFeature = @import("feature/ArmFeature.zig").ArmFeature;
pub const AvrFeature = @import("feature/AvrFeature.zig").AvrFeature;
pub const BpfFeature = @import("feature/BpfFeature.zig").BpfFeature;
pub const HexagonFeature = @import("feature/HexagonFeature.zig").HexagonFeature; pub const MipsFeature = @import("feature/MipsFeature.zig").MipsFeature;
pub const Msp430Feature = @import("feature/Msp430Feature.zig").Msp430Feature;
pub const NvptxFeature = @import("feature/NvptxFeature.zig").NvptxFeature;
pub const PowerPcFeature = @import("feature/PowerPcFeature.zig").PowerPcFeature;
pub const RiscVFeature = @import("feature/RiscVFeature.zig").RiscVFeature;
pub const SparcFeature = @import("feature/SparcFeature.zig").SparcFeature;
pub const SystemZFeature = @import("feature/SystemZFeature.zig").SystemZFeature;
pub const WebAssemblyFeature = @import("feature/WebAssemblyFeature.zig").WebAssemblyFeature;
pub const X86Feature = @import("feature/X86Feature.zig").X86Feature;
pub const EmptyFeature = @import("feature/empty.zig").EmptyFeature;
pub fn ArchFeature(comptime arch: @TagType(Arch)) type {
return switch (arch) {
.arm, .armeb, .thumb, .thumbeb => ArmFeature,
.aarch64, .aarch64_be, .aarch64_32 => AArch64Feature,
.avr => AvrFeature,
.bpfel, .bpfeb => BpfFeature,
.hexagon => HexagonFeature,
.mips, .mipsel, .mips64, .mips64el => MipsFeature,
.msp430 => Msp430Feature,
.powerpc, .powerpc64, .powerpc64le => PowerPcFeature,
.amdgcn => AmdGpuFeature,
.riscv32, .riscv64 => RiscVFeature,
.sparc, .sparcv9, .sparcel => SparcFeature,
.s390x => SystemZFeature,
.i386, .x86_64 => X86Feature,
.nvptx, .nvptx64 => NvptxFeature,
.wasm32, .wasm64 => WebAssemblyFeature,
else => EmptyFeature,
};
}
pub fn ArchFeatureInfo(comptime arch: @TagType(Arch)) type {
return FeatureInfo(ArchFeature(arch));
}
pub fn FeatureInfo(comptime EnumType: type) type {
return struct {
value: EnumType,
name: []const u8,
description: []const u8,
llvm_name: []const u8,
subfeatures: []const EnumType,
const Self = @This();
pub fn create(value: EnumType, name: []const u8, description: []const u8, llvm_name: []const u8) Self {
return Self {
.value = value,
.name = name,
.description = description,
.llvm_name = llvm_name,
.subfeatures = &[_]EnumType{},
};
}
pub fn createWithSubfeatures(value: EnumType, name: []const u8, description: []const u8, llvm_name: []const u8, subfeatures: []const EnumType) Self {
return Self {
.value = value,
.name = name,
.description = description,
.llvm_name = llvm_name,
.subfeatures = subfeatures,
};
}
};
}

750
lib/std/target/feature/AArch64Feature.zig
View File

@@ -1,750 +0,0 @@
const FeatureInfo = @import("std").target.feature.FeatureInfo;
pub const AArch64Feature = enum {
Aes,
Am,
AggressiveFma,
Altnzcv,
AlternateSextloadCvtF32Pattern,
ArithBccFusion,
ArithCbzFusion,
BalanceFpOps,
Bti,
Ccidx,
Ccpp,
Crc,
Ccdp,
CallSavedX8,
CallSavedX9,
CallSavedX10,
CallSavedX11,
CallSavedX12,
CallSavedX13,
CallSavedX14,
CallSavedX15,
CallSavedX18,
Complxnum,
Crypto,
CustomCheapAsMove,
Dit,
DisableLatencySchedHeuristic,
Dotprod,
Ete,
ExynosCheapAsMove,
Fmi,
Fp16fml,
FpArmv8,
Fptoint,
Force32bitJumpTables,
Fullfp16,
FuseAes,
FuseAddress,
FuseArithLogic,
FuseCsel,
FuseCryptoEor,
FuseLiterals,
Jsconv,
Lor,
Lse,
LslFast,
Mpam,
Mte,
Neon,
Nv,
NoNegImmediates,
Pa,
Pan,
PanRwv,
Perfmon,
UsePostraScheduler,
Predres,
PredictableSelectExpensive,
Uaops,
Ras,
Rasv8_4,
Rcpc,
RcpcImmo,
Rdm,
Rand,
ReserveX1,
ReserveX2,
ReserveX3,
ReserveX4,
ReserveX5,
ReserveX6,
ReserveX7,
ReserveX9,
ReserveX10,
ReserveX11,
ReserveX12,
ReserveX13,
ReserveX14,
ReserveX15,
ReserveX18,
ReserveX20,
ReserveX21,
ReserveX22,
ReserveX23,
ReserveX24,
ReserveX25,
ReserveX26,
ReserveX27,
ReserveX28,
Sb,
Sel2,
Sha2,
Sha3,
Sm4,
Spe,
Ssbs,
Sve,
Sve2,
Sve2Aes,
Sve2Bitperm,
Sve2Sha3,
Sve2Sm4,
SlowMisaligned128store,
SlowPaired128,
SlowStrqroStore,
Specrestrict,
StrictAlign,
TlbRmi,
Tme,
Tracev84,
Trbe,
TaggedGlobals,
UseAa,
TpidrEl1,
TpidrEl2,
TpidrEl3,
UseReciprocalSquareRoot,
Vh,
Zcm,
Zcz,
ZczFp,
ZczFpWorkaround,
ZczGp,
V81a,
V82a,
V83a,
V84a,
V85a,
A35,
A53,
A55,
A57,
A65,
A72,
A73,
A75,
A76,
Cyclone,
Exynosm1,
Exynosm2,
Exynosm3,
Exynosm4,
Falkor,
Kryo,
Neoversee1,
Neoversen1,
Saphira,
Tsv110,
Thunderx,
Thunderx2t99,
Thunderxt81,
Thunderxt83,
Thunderxt88,
pub fn getInfo(self: @This()) FeatureInfo(@This()) {
return feature_infos[@enumToInt(self)];
}
pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
FeatureInfo(@This()).createWithSubfeatures(.Aes, "aes", "Enable AES support", "aes", &[_]@This() {
.FpArmv8,
}),
FeatureInfo(@This()).create(.Am, "am", "Enable v8.4-A Activity Monitors extension", "am"),
FeatureInfo(@This()).create(.AggressiveFma, "aggressive-fma", "Enable Aggressive FMA for floating-point.", "aggressive-fma"),
FeatureInfo(@This()).create(.Altnzcv, "altnzcv", "Enable alternative NZCV format for floating point comparisons", "altnzcv"),
FeatureInfo(@This()).create(.AlternateSextloadCvtF32Pattern, "alternate-sextload-cvt-f32-pattern", "Use alternative pattern for sextload convert to f32", "alternate-sextload-cvt-f32-pattern"),
FeatureInfo(@This()).create(.ArithBccFusion, "arith-bcc-fusion", "CPU fuses arithmetic+bcc operations", "arith-bcc-fusion"),
FeatureInfo(@This()).create(.ArithCbzFusion, "arith-cbz-fusion", "CPU fuses arithmetic + cbz/cbnz operations", "arith-cbz-fusion"),
FeatureInfo(@This()).create(.BalanceFpOps, "balance-fp-ops", "balance mix of odd and even D-registers for fp multiply(-accumulate) ops", "balance-fp-ops"),
FeatureInfo(@This()).create(.Bti, "bti", "Enable Branch Target Identification", "bti"),
FeatureInfo(@This()).create(.Ccidx, "ccidx", "Enable v8.3-A Extend of the CCSIDR number of sets", "ccidx"),
FeatureInfo(@This()).create(.Ccpp, "ccpp", "Enable v8.2 data Cache Clean to Point of Persistence", "ccpp"),
FeatureInfo(@This()).create(.Crc, "crc", "Enable ARMv8 CRC-32 checksum instructions", "crc"),
FeatureInfo(@This()).create(.Ccdp, "ccdp", "Enable v8.5 Cache Clean to Point of Deep Persistence", "ccdp"),
FeatureInfo(@This()).create(.CallSavedX8, "call-saved-x8", "Make X8 callee saved.", "call-saved-x8"),
FeatureInfo(@This()).create(.CallSavedX9, "call-saved-x9", "Make X9 callee saved.", "call-saved-x9"),
FeatureInfo(@This()).create(.CallSavedX10, "call-saved-x10", "Make X10 callee saved.", "call-saved-x10"),
FeatureInfo(@This()).create(.CallSavedX11, "call-saved-x11", "Make X11 callee saved.", "call-saved-x11"),
FeatureInfo(@This()).create(.CallSavedX12, "call-saved-x12", "Make X12 callee saved.", "call-saved-x12"),
FeatureInfo(@This()).create(.CallSavedX13, "call-saved-x13", "Make X13 callee saved.", "call-saved-x13"),
FeatureInfo(@This()).create(.CallSavedX14, "call-saved-x14", "Make X14 callee saved.", "call-saved-x14"),
FeatureInfo(@This()).create(.CallSavedX15, "call-saved-x15", "Make X15 callee saved.", "call-saved-x15"),
FeatureInfo(@This()).create(.CallSavedX18, "call-saved-x18", "Make X18 callee saved.", "call-saved-x18"),
FeatureInfo(@This()).createWithSubfeatures(.Complxnum, "complxnum", "Enable v8.3-A Floating-point complex number support", "complxnum", &[_]@This() {
.FpArmv8,
}),
FeatureInfo(@This()).createWithSubfeatures(.Crypto, "crypto", "Enable cryptographic instructions", "crypto", &[_]@This() {
.FpArmv8,
}),
FeatureInfo(@This()).create(.CustomCheapAsMove, "custom-cheap-as-move", "Use custom handling of cheap instructions", "custom-cheap-as-move"),
FeatureInfo(@This()).create(.Dit, "dit", "Enable v8.4-A Data Independent Timing instructions", "dit"),
FeatureInfo(@This()).create(.DisableLatencySchedHeuristic, "disable-latency-sched-heuristic", "Disable latency scheduling heuristic", "disable-latency-sched-heuristic"),
FeatureInfo(@This()).create(.Dotprod, "dotprod", "Enable dot product support", "dotprod"),
FeatureInfo(@This()).createWithSubfeatures(.Ete, "ete", "Enable Embedded Trace Extension", "ete", &[_]@This() {
.Trbe,
}),
FeatureInfo(@This()).createWithSubfeatures(.ExynosCheapAsMove, "exynos-cheap-as-move", "Use Exynos specific handling of cheap instructions", "exynos-cheap-as-move", &[_]@This() {
.CustomCheapAsMove,
}),
FeatureInfo(@This()).create(.Fmi, "fmi", "Enable v8.4-A Flag Manipulation Instructions", "fmi"),
FeatureInfo(@This()).createWithSubfeatures(.Fp16fml, "fp16fml", "Enable FP16 FML instructions", "fp16fml", &[_]@This() {
.FpArmv8,
}),
FeatureInfo(@This()).create(.FpArmv8, "fp-armv8", "Enable ARMv8 FP", "fp-armv8"),
FeatureInfo(@This()).create(.Fptoint, "fptoint", "Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int", "fptoint"),
FeatureInfo(@This()).create(.Force32bitJumpTables, "force-32bit-jump-tables", "Force jump table entries to be 32-bits wide except at MinSize", "force-32bit-jump-tables"),
FeatureInfo(@This()).createWithSubfeatures(.Fullfp16, "fullfp16", "Full FP16", "fullfp16", &[_]@This() {
.FpArmv8,
}),
FeatureInfo(@This()).create(.FuseAes, "fuse-aes", "CPU fuses AES crypto operations", "fuse-aes"),
FeatureInfo(@This()).create(.FuseAddress, "fuse-address", "CPU fuses address generation and memory operations", "fuse-address"),
FeatureInfo(@This()).create(.FuseArithLogic, "fuse-arith-logic", "CPU fuses arithmetic and logic operations", "fuse-arith-logic"),
FeatureInfo(@This()).create(.FuseCsel, "fuse-csel", "CPU fuses conditional select operations", "fuse-csel"),
FeatureInfo(@This()).create(.FuseCryptoEor, "fuse-crypto-eor", "CPU fuses AES/PMULL and EOR operations", "fuse-crypto-eor"),
FeatureInfo(@This()).create(.FuseLiterals, "fuse-literals", "CPU fuses literal generation operations", "fuse-literals"),
FeatureInfo(@This()).createWithSubfeatures(.Jsconv, "jsconv", "Enable v8.3-A JavaScript FP conversion enchancement", "jsconv", &[_]@This() {
.FpArmv8,
}),
FeatureInfo(@This()).create(.Lor, "lor", "Enables ARM v8.1 Limited Ordering Regions extension", "lor"),
FeatureInfo(@This()).create(.Lse, "lse", "Enable ARMv8.1 Large System Extension (LSE) atomic instructions", "lse"),
FeatureInfo(@This()).create(.LslFast, "lsl-fast", "CPU has a fastpath logical shift of up to 3 places", "lsl-fast"),
FeatureInfo(@This()).create(.Mpam, "mpam", "Enable v8.4-A Memory system Partitioning and Monitoring extension", "mpam"),
FeatureInfo(@This()).create(.Mte, "mte", "Enable Memory Tagging Extension", "mte"),
FeatureInfo(@This()).createWithSubfeatures(.Neon, "neon", "Enable Advanced SIMD instructions", "neon", &[_]@This() {
.FpArmv8,
}),
FeatureInfo(@This()).create(.Nv, "nv", "Enable v8.4-A Nested Virtualization Enchancement", "nv"),
FeatureInfo(@This()).create(.NoNegImmediates, "no-neg-immediates", "Convert immediates and instructions to their negated or complemented equivalent when the immediate does not fit in the encoding.", "no-neg-immediates"),
FeatureInfo(@This()).create(.Pa, "pa", "Enable v8.3-A Pointer Authentication enchancement", "pa"),
FeatureInfo(@This()).create(.Pan, "pan", "Enables ARM v8.1 Privileged Access-Never extension", "pan"),
FeatureInfo(@This()).createWithSubfeatures(.PanRwv, "pan-rwv", "Enable v8.2 PAN s1e1R and s1e1W Variants", "pan-rwv", &[_]@This() {
.Pan,
}),
FeatureInfo(@This()).create(.Perfmon, "perfmon", "Enable ARMv8 PMUv3 Performance Monitors extension", "perfmon"),
FeatureInfo(@This()).create(.UsePostraScheduler, "use-postra-scheduler", "Schedule again after register allocation", "use-postra-scheduler"),
FeatureInfo(@This()).create(.Predres, "predres", "Enable v8.5a execution and data prediction invalidation instructions", "predres"),
FeatureInfo(@This()).create(.PredictableSelectExpensive, "predictable-select-expensive", "Prefer likely predicted branches over selects", "predictable-select-expensive"),
FeatureInfo(@This()).create(.Uaops, "uaops", "Enable v8.2 UAO PState", "uaops"),
FeatureInfo(@This()).create(.Ras, "ras", "Enable ARMv8 Reliability, Availability and Serviceability Extensions", "ras"),
FeatureInfo(@This()).createWithSubfeatures(.Rasv8_4, "rasv8_4", "Enable v8.4-A Reliability, Availability and Serviceability extension", "rasv8_4", &[_]@This() {
.Ras,
}),
FeatureInfo(@This()).create(.Rcpc, "rcpc", "Enable support for RCPC extension", "rcpc"),
FeatureInfo(@This()).createWithSubfeatures(.RcpcImmo, "rcpc-immo", "Enable v8.4-A RCPC instructions with Immediate Offsets", "rcpc-immo", &[_]@This() {
.Rcpc,
}),
FeatureInfo(@This()).create(.Rdm, "rdm", "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions", "rdm"),
FeatureInfo(@This()).create(.Rand, "rand", "Enable Random Number generation instructions", "rand"),
FeatureInfo(@This()).create(.ReserveX1, "reserve-x1", "Reserve X1, making it unavailable as a GPR", "reserve-x1"),
FeatureInfo(@This()).create(.ReserveX2, "reserve-x2", "Reserve X2, making it unavailable as a GPR", "reserve-x2"),
FeatureInfo(@This()).create(.ReserveX3, "reserve-x3", "Reserve X3, making it unavailable as a GPR", "reserve-x3"),
FeatureInfo(@This()).create(.ReserveX4, "reserve-x4", "Reserve X4, making it unavailable as a GPR", "reserve-x4"),
FeatureInfo(@This()).create(.ReserveX5, "reserve-x5", "Reserve X5, making it unavailable as a GPR", "reserve-x5"),
FeatureInfo(@This()).create(.ReserveX6, "reserve-x6", "Reserve X6, making it unavailable as a GPR", "reserve-x6"),
FeatureInfo(@This()).create(.ReserveX7, "reserve-x7", "Reserve X7, making it unavailable as a GPR", "reserve-x7"),
FeatureInfo(@This()).create(.ReserveX9, "reserve-x9", "Reserve X9, making it unavailable as a GPR", "reserve-x9"),
FeatureInfo(@This()).create(.ReserveX10, "reserve-x10", "Reserve X10, making it unavailable as a GPR", "reserve-x10"),
FeatureInfo(@This()).create(.ReserveX11, "reserve-x11", "Reserve X11, making it unavailable as a GPR", "reserve-x11"),
FeatureInfo(@This()).create(.ReserveX12, "reserve-x12", "Reserve X12, making it unavailable as a GPR", "reserve-x12"),
FeatureInfo(@This()).create(.ReserveX13, "reserve-x13", "Reserve X13, making it unavailable as a GPR", "reserve-x13"),
FeatureInfo(@This()).create(.ReserveX14, "reserve-x14", "Reserve X14, making it unavailable as a GPR", "reserve-x14"),
FeatureInfo(@This()).create(.ReserveX15, "reserve-x15", "Reserve X15, making it unavailable as a GPR", "reserve-x15"),
FeatureInfo(@This()).create(.ReserveX18, "reserve-x18", "Reserve X18, making it unavailable as a GPR", "reserve-x18"),
FeatureInfo(@This()).create(.ReserveX20, "reserve-x20", "Reserve X20, making it unavailable as a GPR", "reserve-x20"),
FeatureInfo(@This()).create(.ReserveX21, "reserve-x21", "Reserve X21, making it unavailable as a GPR", "reserve-x21"),
FeatureInfo(@This()).create(.ReserveX22, "reserve-x22", "Reserve X22, making it unavailable as a GPR", "reserve-x22"),
FeatureInfo(@This()).create(.ReserveX23, "reserve-x23", "Reserve X23, making it unavailable as a GPR", "reserve-x23"),
FeatureInfo(@This()).create(.ReserveX24, "reserve-x24", "Reserve X24, making it unavailable as a GPR", "reserve-x24"),
FeatureInfo(@This()).create(.ReserveX25, "reserve-x25", "Reserve X25, making it unavailable as a GPR", "reserve-x25"),
FeatureInfo(@This()).create(.ReserveX26, "reserve-x26", "Reserve X26, making it unavailable as a GPR", "reserve-x26"),
FeatureInfo(@This()).create(.ReserveX27, "reserve-x27", "Reserve X27, making it unavailable as a GPR", "reserve-x27"),
FeatureInfo(@This()).create(.ReserveX28, "reserve-x28", "Reserve X28, making it unavailable as a GPR", "reserve-x28"),
FeatureInfo(@This()).create(.Sb, "sb", "Enable v8.5 Speculation Barrier", "sb"),
FeatureInfo(@This()).create(.Sel2, "sel2", "Enable v8.4-A Secure Exception Level 2 extension", "sel2"),
FeatureInfo(@This()).createWithSubfeatures(.Sha2, "sha2", "Enable SHA1 and SHA256 support", "sha2", &[_]@This() {
.FpArmv8,
}),
FeatureInfo(@This()).createWithSubfeatures(.Sha3, "sha3", "Enable SHA512 and SHA3 support", "sha3", &[_]@This() {
.FpArmv8,
}),
FeatureInfo(@This()).createWithSubfeatures(.Sm4, "sm4", "Enable SM3 and SM4 support", "sm4", &[_]@This() {
.FpArmv8,
}),
FeatureInfo(@This()).create(.Spe, "spe", "Enable Statistical Profiling extension", "spe"),
FeatureInfo(@This()).create(.Ssbs, "ssbs", "Enable Speculative Store Bypass Safe bit", "ssbs"),
FeatureInfo(@This()).create(.Sve, "sve", "Enable Scalable Vector Extension (SVE) instructions", "sve"),
FeatureInfo(@This()).createWithSubfeatures(.Sve2, "sve2", "Enable Scalable Vector Extension 2 (SVE2) instructions", "sve2", &[_]@This() {
.Sve,
}),
FeatureInfo(@This()).createWithSubfeatures(.Sve2Aes, "sve2-aes", "Enable AES SVE2 instructions", "sve2-aes", &[_]@This() {
.FpArmv8,
.Sve,
}),
FeatureInfo(@This()).createWithSubfeatures(.Sve2Bitperm, "sve2-bitperm", "Enable bit permutation SVE2 instructions", "sve2-bitperm", &[_]@This() {
.Sve,
}),
FeatureInfo(@This()).createWithSubfeatures(.Sve2Sha3, "sve2-sha3", "Enable SHA3 SVE2 instructions", "sve2-sha3", &[_]@This() {
.FpArmv8,
.Sve,
}),
FeatureInfo(@This()).createWithSubfeatures(.Sve2Sm4, "sve2-sm4", "Enable SM4 SVE2 instructions", "sve2-sm4", &[_]@This() {
.FpArmv8,
.Sve,
}),
FeatureInfo(@This()).create(.SlowMisaligned128store, "slow-misaligned-128store", "Misaligned 128 bit stores are slow", "slow-misaligned-128store"),
FeatureInfo(@This()).create(.SlowPaired128, "slow-paired-128", "Paired 128 bit loads and stores are slow", "slow-paired-128"),
FeatureInfo(@This()).create(.SlowStrqroStore, "slow-strqro-store", "STR of Q register with register offset is slow", "slow-strqro-store"),
FeatureInfo(@This()).create(.Specrestrict, "specrestrict", "Enable architectural speculation restriction", "specrestrict"),
FeatureInfo(@This()).create(.StrictAlign, "strict-align", "Disallow all unaligned memory access", "strict-align"),
FeatureInfo(@This()).create(.TlbRmi, "tlb-rmi", "Enable v8.4-A TLB Range and Maintenance Instructions", "tlb-rmi"),
FeatureInfo(@This()).create(.Tme, "tme", "Enable Transactional Memory Extension", "tme"),
FeatureInfo(@This()).create(.Tracev84, "tracev8.4", "Enable v8.4-A Trace extension", "tracev8.4"),
FeatureInfo(@This()).create(.Trbe, "trbe", "Enable Trace Buffer Extension", "trbe"),
FeatureInfo(@This()).create(.TaggedGlobals, "tagged-globals", "Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits", "tagged-globals"),
FeatureInfo(@This()).create(.UseAa, "use-aa", "Use alias analysis during codegen", "use-aa"),
FeatureInfo(@This()).create(.TpidrEl1, "tpidr-el1", "Permit use of TPIDR_EL1 for the TLS base", "tpidr-el1"),
FeatureInfo(@This()).create(.TpidrEl2, "tpidr-el2", "Permit use of TPIDR_EL2 for the TLS base", "tpidr-el2"),
FeatureInfo(@This()).create(.TpidrEl3, "tpidr-el3", "Permit use of TPIDR_EL3 for the TLS base", "tpidr-el3"),
FeatureInfo(@This()).create(.UseReciprocalSquareRoot, "use-reciprocal-square-root", "Use the reciprocal square root approximation", "use-reciprocal-square-root"),
FeatureInfo(@This()).create(.Vh, "vh", "Enables ARM v8.1 Virtual Host extension", "vh"),
FeatureInfo(@This()).create(.Zcm, "zcm", "Has zero-cycle register moves", "zcm"),
FeatureInfo(@This()).createWithSubfeatures(.Zcz, "zcz", "Has zero-cycle zeroing instructions", "zcz", &[_]@This() {
.ZczGp,
.ZczFp,
}),
FeatureInfo(@This()).create(.ZczFp, "zcz-fp", "Has zero-cycle zeroing instructions for FP registers", "zcz-fp"),
FeatureInfo(@This()).create(.ZczFpWorkaround, "zcz-fp-workaround", "The zero-cycle floating-point zeroing instruction has a bug", "zcz-fp-workaround"),
FeatureInfo(@This()).create(.ZczGp, "zcz-gp", "Has zero-cycle zeroing instructions for generic registers", "zcz-gp"),
FeatureInfo(@This()).createWithSubfeatures(.V81a, "v8.1a", "Support ARM v8.1a instructions", "v8.1a", &[_]@This() {
.Lse,
.Rdm,
.Crc,
.Lor,
.Pan,
.Vh,
}),
FeatureInfo(@This()).createWithSubfeatures(.V82a, "v8.2a", "Support ARM v8.2a instructions", "v8.2a", &[_]@This() {
.Lse,
.Rdm,
.Pan,
.Crc,
.Lor,
.Uaops,
.Ras,
.Ccpp,
.Vh,
}),
FeatureInfo(@This()).createWithSubfeatures(.V83a, "v8.3a", "Support ARM v8.3a instructions", "v8.3a", &[_]@This() {
.Lse,
.Vh,
.Pa,
.Rdm,
.Pan,
.Crc,
.Lor,
.Uaops,
.Ras,
.Rcpc,
.Ccpp,
.Ccidx,
.FpArmv8,
}),
FeatureInfo(@This()).createWithSubfeatures(.V84a, "v8.4a", "Support ARM v8.4a instructions", "v8.4a", &[_]@This() {
.Rdm,
.Dit,
.Am,
.Ras,
.Rcpc,
.Sel2,
.Ccpp,
.Pa,
.Pan,
.Uaops,
.Tracev84,
.Mpam,
.Lse,
.Nv,
.Dotprod,
.TlbRmi,
.Lor,
.Ccidx,
.FpArmv8,
.Crc,
.Fmi,
.Vh,
}),
FeatureInfo(@This()).createWithSubfeatures(.V85a, "v8.5a", "Support ARM v8.5a instructions", "v8.5a", &[_]@This() {
.Vh,
.Rdm,
.Dit,
.Am,
.Ssbs,
.Specrestrict,
.Ras,
.Rcpc,
.Sel2,
.Ccpp,
.Pa,
.Bti,
.Ccdp,
.Pan,
.Uaops,
.Tracev84,
.Mpam,
.Lse,
.Sb,
.Nv,
.Altnzcv,
.Dotprod,
.TlbRmi,
.Lor,
.Ccidx,
.Predres,
.Crc,
.Fptoint,
.Fmi,
.FpArmv8,
}),
FeatureInfo(@This()).createWithSubfeatures(.A35, "a35", "Cortex-A35 ARM processors", "a35", &[_]@This() {
.Perfmon,
.FpArmv8,
.Crc,
}),
FeatureInfo(@This()).createWithSubfeatures(.A53, "a53", "Cortex-A53 ARM processors", "a53", &[_]@This() {
.Perfmon,
.UsePostraScheduler,
.Crc,
.CustomCheapAsMove,
.BalanceFpOps,
.UseAa,
.FpArmv8,
.FuseAes,
}),
FeatureInfo(@This()).createWithSubfeatures(.A55, "a55", "Cortex-A55 ARM processors", "a55", &[_]@This() {
.Lse,
.Vh,
.Rdm,
.Perfmon,
.Pan,
.Dotprod,
.Crc,
.Lor,
.Uaops,
.Ras,
.Rcpc,
.Ccpp,
.FpArmv8,
.FuseAes,
}),
FeatureInfo(@This()).createWithSubfeatures(.A57, "a57", "Cortex-A57 ARM processors", "a57", &[_]@This() {
.Perfmon,
.UsePostraScheduler,
.Crc,
.PredictableSelectExpensive,
.CustomCheapAsMove,
.BalanceFpOps,
.FuseLiterals,
.FpArmv8,
.FuseAes,
}),
FeatureInfo(@This()).createWithSubfeatures(.A65, "a65", "Cortex-A65 ARM processors", "a65", &[_]@This() {
.Lse,
.Vh,
.Rdm,
.Pan,
.Dotprod,
.Crc,
.Ssbs,
.Lor,
.Uaops,
.Ras,
.Rcpc,
.Ccpp,
.FpArmv8,
}),
FeatureInfo(@This()).createWithSubfeatures(.A72, "a72", "Cortex-A72 ARM processors", "a72", &[_]@This() {
.Perfmon,
.FpArmv8,
.Crc,
.FuseAes,
}),
FeatureInfo(@This()).createWithSubfeatures(.A73, "a73", "Cortex-A73 ARM processors", "a73", &[_]@This() {
.Perfmon,
.FpArmv8,
.Crc,
.FuseAes,
}),
FeatureInfo(@This()).createWithSubfeatures(.A75, "a75", "Cortex-A75 ARM processors", "a75", &[_]@This() {
.Lse,
.Vh,
.Rdm,
.Perfmon,
.Pan,
.Dotprod,
.Crc,
.Lor,
.Uaops,
.Ras,
.Rcpc,
.Ccpp,
.FpArmv8,
.FuseAes,
}),
FeatureInfo(@This()).createWithSubfeatures(.A76, "a76", "Cortex-A76 ARM processors", "a76", &[_]@This() {
.Lse,
.Vh,
.Rdm,
.Pan,
.Dotprod,
.Crc,
.Ssbs,
.Lor,
.Uaops,
.Ras,
.Rcpc,
.Ccpp,
.FpArmv8,
}),
FeatureInfo(@This()).createWithSubfeatures(.Cyclone, "cyclone", "Cyclone", "cyclone", &[_]@This() {
.ArithBccFusion,
.ArithCbzFusion,
.ZczFp,
.AlternateSextloadCvtF32Pattern,
.DisableLatencySchedHeuristic,
.Perfmon,
.ZczGp,
.ZczFpWorkaround,
.Zcm,
.FpArmv8,
.FuseCryptoEor,
.FuseAes,
}),
FeatureInfo(@This()).createWithSubfeatures(.Exynosm1, "exynosm1", "Samsung Exynos-M1 processors", "exynosm1", &[_]@This() {
.ZczFp,
.Perfmon,
.UsePostraScheduler,
.Crc,
.UseReciprocalSquareRoot,
.CustomCheapAsMove,
.Force32bitJumpTables,
.SlowMisaligned128store,
.FpArmv8,
.SlowPaired128,
.FuseAes,
}),
FeatureInfo(@This()).createWithSubfeatures(.Exynosm2, "exynosm2", "Samsung Exynos-M2 processors", "exynosm2", &[_]@This() {
.ZczFp,
.Perfmon,
.UsePostraScheduler,
.Crc,
.CustomCheapAsMove,
.Force32bitJumpTables,
.SlowMisaligned128store,
.FpArmv8,
.SlowPaired128,
.FuseAes,
}),
FeatureInfo(@This()).createWithSubfeatures(.Exynosm3, "exynosm3", "Samsung Exynos-M3 processors", "exynosm3", &[_]@This() {
.FuseCsel,
.ZczFp,
.Perfmon,
.UsePostraScheduler,
.Crc,
.PredictableSelectExpensive,
.CustomCheapAsMove,
.Force32bitJumpTables,
.FuseLiterals,
.FuseAddress,
.LslFast,
.FpArmv8,
.FuseAes,
}),
FeatureInfo(@This()).createWithSubfeatures(.Exynosm4, "exynosm4", "Samsung Exynos-M4 processors", "exynosm4", &[_]@This() {
.ArithBccFusion,
.Vh,
.ArithCbzFusion,
.ZczFp,
.Rdm,
.UsePostraScheduler,
.Ras,
.Force32bitJumpTables,
.Ccpp,
.FuseCsel,
.Pan,
.Uaops,
.FuseLiterals,
.LslFast,
.Lse,
.Perfmon,
.Dotprod,
.Lor,
.FuseArithLogic,
.Crc,
.CustomCheapAsMove,
.FuseAddress,
.ZczGp,
.FpArmv8,
.FuseAes,
}),
FeatureInfo(@This()).createWithSubfeatures(.Falkor, "falkor", "Qualcomm Falkor processors", "falkor", &[_]@This() {
.ZczFp,
.Rdm,
.Perfmon,
.UsePostraScheduler,
.Crc,
.PredictableSelectExpensive,
.CustomCheapAsMove,
.ZczGp,
.FpArmv8,
.SlowStrqroStore,
.LslFast,
}),
FeatureInfo(@This()).createWithSubfeatures(.Kryo, "kryo", "Qualcomm Kryo processors", "kryo", &[_]@This() {
.ZczFp,
.Perfmon,
.UsePostraScheduler,
.Crc,
.PredictableSelectExpensive,
.CustomCheapAsMove,
.ZczGp,
.FpArmv8,
.LslFast,
}),
FeatureInfo(@This()).createWithSubfeatures(.Neoversee1, "neoversee1", "Neoverse E1 ARM processors", "neoversee1", &[_]@This() {
.Lse,
.Vh,
.Rdm,
.Pan,
.Dotprod,
.Crc,
.Ssbs,
.Lor,
.Uaops,
.Ras,
.Rcpc,
.Ccpp,
.FpArmv8,
}),
FeatureInfo(@This()).createWithSubfeatures(.Neoversen1, "neoversen1", "Neoverse N1 ARM processors", "neoversen1", &[_]@This() {
.Lse,
.Spe,
.Vh,
.Rdm,
.Pan,
.Dotprod,
.Crc,
.Ssbs,
.Lor,
.Uaops,
.Ras,
.Rcpc,
.Ccpp,
.FpArmv8,
}),
FeatureInfo(@This()).createWithSubfeatures(.Saphira, "saphira", "Qualcomm Saphira processors", "saphira", &[_]@This() {
.Spe,
.Vh,
.ZczFp,
.Rdm,
.UsePostraScheduler,
.Dit,
.Am,
.Ras,
.Rcpc,
.Sel2,
.Ccpp,
.Pa,
.Pan,
.Uaops,
.Tracev84,
.Mpam,
.LslFast,
.Lse,
.Nv,
.Perfmon,
.Dotprod,
.TlbRmi,
.Lor,
.Ccidx,
.PredictableSelectExpensive,
.Crc,
.CustomCheapAsMove,
.Fmi,
.ZczGp,
.FpArmv8,
}),
FeatureInfo(@This()).createWithSubfeatures(.Tsv110, "tsv110", "HiSilicon TS-V110 processors", "tsv110", &[_]@This() {
.Lse,
.Spe,
.Vh,
.Rdm,
.Perfmon,
.UsePostraScheduler,
.Pan,
.Dotprod,
.Crc,
.Lor,
.Uaops,
.CustomCheapAsMove,
.Ras,
.Ccpp,
.FpArmv8,
.FuseAes,
}),
FeatureInfo(@This()).createWithSubfeatures(.Thunderx, "thunderx", "Cavium ThunderX processors", "thunderx", &[_]@This() {
.Perfmon,
.UsePostraScheduler,
.Crc,
.FpArmv8,
.PredictableSelectExpensive,
}),
FeatureInfo(@This()).createWithSubfeatures(.Thunderx2t99, "thunderx2t99", "Cavium ThunderX2 processors", "thunderx2t99", &[_]@This() {
.Lse,
.ArithBccFusion,
.Vh,
.Rdm,
.UsePostraScheduler,
.Crc,
.Lor,
.Pan,
.AggressiveFma,
.FpArmv8,
.PredictableSelectExpensive,
}),
FeatureInfo(@This()).createWithSubfeatures(.Thunderxt81, "thunderxt81", "Cavium ThunderX processors", "thunderxt81", &[_]@This() {
.Perfmon,
.UsePostraScheduler,
.Crc,
.FpArmv8,
.PredictableSelectExpensive,
}),
FeatureInfo(@This()).createWithSubfeatures(.Thunderxt83, "thunderxt83", "Cavium ThunderX processors", "thunderxt83", &[_]@This() {
.Perfmon,
.UsePostraScheduler,
.Crc,
.FpArmv8,
.PredictableSelectExpensive,
}),
FeatureInfo(@This()).createWithSubfeatures(.Thunderxt88, "thunderxt88", "Cavium ThunderX processors", "thunderxt88", &[_]@This() {
.Perfmon,
.UsePostraScheduler,
.Crc,
.FpArmv8,
.PredictableSelectExpensive,
}),
};
};

343
lib/std/target/feature/AmdGpuFeature.zig
View File

@@ -1,343 +0,0 @@
const FeatureInfo = @import("std").target.feature.FeatureInfo;
pub const AmdGpuFeature = enum {
BitInsts16,
AddNoCarryInsts,
ApertureRegs,
AtomicFaddInsts,
AutoWaitcntBeforeBarrier,
CiInsts,
CodeObjectV3,
Cumode,
DlInsts,
Dpp,
Dpp8,
NoSramEccSupport,
NoXnackSupport,
Dot1Insts,
Dot2Insts,
Dot3Insts,
Dot4Insts,
Dot5Insts,
Dot6Insts,
DumpCode,
Dumpcode,
EnableDs128,
LoadStoreOpt,
EnablePrtStrictNull,
SiScheduler,
UnsafeDsOffsetFolding,
Fmaf,
Fp16Denormals,
Fp32Denormals,
Fp64,
Fp64Denormals,
Fp64Fp16Denormals,
FpExceptions,
FastFmaf,
FlatAddressSpace,
FlatForGlobal,
FlatGlobalInsts,
FlatInstOffsets,
FlatScratchInsts,
FlatSegmentOffsetBug,
FmaMixInsts,
Gcn3Encoding,
Gfx7Gfx8Gfx9Insts,
Gfx8Insts,
Gfx9,
Gfx9Insts,
Gfx10,
Gfx10Insts,
InstFwdPrefetchBug,
IntClampInsts,
Inv2piInlineImm,
Ldsbankcount16,
Ldsbankcount32,
LdsBranchVmemWarHazard,
LdsMisalignedBug,
Localmemorysize0,
Localmemorysize32768,
Localmemorysize65536,
MaiInsts,
MfmaInlineLiteralBug,
MimgR128,
MadMixInsts,
MaxPrivateElementSize4,
MaxPrivateElementSize8,
MaxPrivateElementSize16,
Movrel,
NsaEncoding,
NsaToVmemBug,
NoDataDepHazard,
NoSdstCmpx,
Offset3fBug,
PkFmacF16Inst,
PromoteAlloca,
R128A16,
RegisterBanking,
Sdwa,
SdwaMav,
SdwaOmod,
SdwaOutModsVopc,
SdwaScalar,
SdwaSdst,
SgprInitBug,
SmemToVectorWriteHazard,
SMemrealtime,
SramEcc,
ScalarAtomics,
ScalarFlatScratchInsts,
ScalarStores,
SeaIslands,
SouthernIslands,
TrapHandler,
TrigReducedRange,
UnalignedBufferAccess,
UnalignedScratchAccess,
UnpackedD16Vmem,
VgprIndexMode,
VmemToScalarWriteHazard,
Vop3Literal,
Vop3p,
VcmpxExecWarHazard,
VcmpxPermlaneHazard,
VolcanicIslands,
Vscnt,
Wavefrontsize16,
Wavefrontsize32,
Wavefrontsize64,
Xnack,
HalfRate64Ops,
pub fn getInfo(self: @This()) FeatureInfo(@This()) {
return feature_infos[@enumToInt(self)];
}
pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
FeatureInfo(@This()).create(.BitInsts16, "16-bit-insts", "Has i16/f16 instructions", "16-bit-insts"),
FeatureInfo(@This()).create(.AddNoCarryInsts, "add-no-carry-insts", "Have VALU add/sub instructions without carry out", "add-no-carry-insts"),
FeatureInfo(@This()).create(.ApertureRegs, "aperture-regs", "Has Memory Aperture Base and Size Registers", "aperture-regs"),
FeatureInfo(@This()).create(.AtomicFaddInsts, "atomic-fadd-insts", "Has buffer_atomic_add_f32, buffer_atomic_pk_add_f16, global_atomic_add_f32, global_atomic_pk_add_f16 instructions", "atomic-fadd-insts"),
FeatureInfo(@This()).create(.AutoWaitcntBeforeBarrier, "auto-waitcnt-before-barrier", "Hardware automatically inserts waitcnt before barrier", "auto-waitcnt-before-barrier"),
FeatureInfo(@This()).create(.CiInsts, "ci-insts", "Additional instructions for CI+", "ci-insts"),
FeatureInfo(@This()).create(.CodeObjectV3, "code-object-v3", "Generate code object version 3", "code-object-v3"),
FeatureInfo(@This()).create(.Cumode, "cumode", "Enable CU wavefront execution mode", "cumode"),
FeatureInfo(@This()).create(.DlInsts, "dl-insts", "Has v_fmac_f32 and v_xnor_b32 instructions", "dl-insts"),
FeatureInfo(@This()).create(.Dpp, "dpp", "Support DPP (Data Parallel Primitives) extension", "dpp"),
FeatureInfo(@This()).create(.Dpp8, "dpp8", "Support DPP8 (Data Parallel Primitives) extension", "dpp8"),
FeatureInfo(@This()).create(.NoSramEccSupport, "no-sram-ecc-support", "Hardware does not support SRAM ECC", "no-sram-ecc-support"),
FeatureInfo(@This()).create(.NoXnackSupport, "no-xnack-support", "Hardware does not support XNACK", "no-xnack-support"),
FeatureInfo(@This()).create(.Dot1Insts, "dot1-insts", "Has v_dot4_i32_i8 and v_dot8_i32_i4 instructions", "dot1-insts"),
FeatureInfo(@This()).create(.Dot2Insts, "dot2-insts", "Has v_dot2_f32_f16, v_dot2_i32_i16, v_dot2_u32_u16, v_dot4_u32_u8, v_dot8_u32_u4 instructions", "dot2-insts"),
FeatureInfo(@This()).create(.Dot3Insts, "dot3-insts", "Has v_dot8c_i32_i4 instruction", "dot3-insts"),
FeatureInfo(@This()).create(.Dot4Insts, "dot4-insts", "Has v_dot2c_i32_i16 instruction", "dot4-insts"),
FeatureInfo(@This()).create(.Dot5Insts, "dot5-insts", "Has v_dot2c_f32_f16 instruction", "dot5-insts"),
FeatureInfo(@This()).create(.Dot6Insts, "dot6-insts", "Has v_dot4c_i32_i8 instruction", "dot6-insts"),
FeatureInfo(@This()).create(.DumpCode, "DumpCode", "Dump MachineInstrs in the CodeEmitter", "DumpCode"),
FeatureInfo(@This()).create(.Dumpcode, "dumpcode", "Dump MachineInstrs in the CodeEmitter", "dumpcode"),
FeatureInfo(@This()).create(.EnableDs128, "enable-ds128", "Use ds_{read|write}_b128", "enable-ds128"),
FeatureInfo(@This()).create(.LoadStoreOpt, "load-store-opt", "Enable SI load/store optimizer pass", "load-store-opt"),
FeatureInfo(@This()).create(.EnablePrtStrictNull, "enable-prt-strict-null", "Enable zeroing of result registers for sparse texture fetches", "enable-prt-strict-null"),
FeatureInfo(@This()).create(.SiScheduler, "si-scheduler", "Enable SI Machine Scheduler", "si-scheduler"),
FeatureInfo(@This()).create(.UnsafeDsOffsetFolding, "unsafe-ds-offset-folding", "Force using DS instruction immediate offsets on SI", "unsafe-ds-offset-folding"),
FeatureInfo(@This()).create(.Fmaf, "fmaf", "Enable single precision FMA (not as fast as mul+add, but fused)", "fmaf"),
FeatureInfo(@This()).createWithSubfeatures(.Fp16Denormals, "fp16-denormals", "Enable half precision denormal handling", "fp16-denormals", &[_]@This() {
.Fp64,
}),
FeatureInfo(@This()).create(.Fp32Denormals, "fp32-denormals", "Enable single precision denormal handling", "fp32-denormals"),
FeatureInfo(@This()).create(.Fp64, "fp64", "Enable double precision operations", "fp64"),
FeatureInfo(@This()).createWithSubfeatures(.Fp64Denormals, "fp64-denormals", "Enable double and half precision denormal handling", "fp64-denormals", &[_]@This() {
.Fp64,
}),
FeatureInfo(@This()).createWithSubfeatures(.Fp64Fp16Denormals, "fp64-fp16-denormals", "Enable double and half precision denormal handling", "fp64-fp16-denormals", &[_]@This() {
.Fp64,
}),
FeatureInfo(@This()).create(.FpExceptions, "fp-exceptions", "Enable floating point exceptions", "fp-exceptions"),
FeatureInfo(@This()).create(.FastFmaf, "fast-fmaf", "Assuming f32 fma is at least as fast as mul + add", "fast-fmaf"),
FeatureInfo(@This()).create(.FlatAddressSpace, "flat-address-space", "Support flat address space", "flat-address-space"),
FeatureInfo(@This()).create(.FlatForGlobal, "flat-for-global", "Force to generate flat instruction for global", "flat-for-global"),
FeatureInfo(@This()).create(.FlatGlobalInsts, "flat-global-insts", "Have global_* flat memory instructions", "flat-global-insts"),
FeatureInfo(@This()).create(.FlatInstOffsets, "flat-inst-offsets", "Flat instructions have immediate offset addressing mode", "flat-inst-offsets"),
FeatureInfo(@This()).create(.FlatScratchInsts, "flat-scratch-insts", "Have scratch_* flat memory instructions", "flat-scratch-insts"),
FeatureInfo(@This()).create(.FlatSegmentOffsetBug, "flat-segment-offset-bug", "GFX10 bug, inst_offset ignored in flat segment", "flat-segment-offset-bug"),
FeatureInfo(@This()).create(.FmaMixInsts, "fma-mix-insts", "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions", "fma-mix-insts"),
FeatureInfo(@This()).create(.Gcn3Encoding, "gcn3-encoding", "Encoding format for VI", "gcn3-encoding"),
FeatureInfo(@This()).create(.Gfx7Gfx8Gfx9Insts, "gfx7-gfx8-gfx9-insts", "Instructions shared in GFX7, GFX8, GFX9", "gfx7-gfx8-gfx9-insts"),
FeatureInfo(@This()).create(.Gfx8Insts, "gfx8-insts", "Additional instructions for GFX8+", "gfx8-insts"),
FeatureInfo(@This()).createWithSubfeatures(.Gfx9, "gfx9", "GFX9 GPU generation", "gfx9", &[_]@This() {
.ApertureRegs,
.IntClampInsts,
.SdwaOmod,
.SdwaScalar,
.AddNoCarryInsts,
.ScalarAtomics,
.SMemrealtime,
.Gcn3Encoding,
.CiInsts,
.FlatAddressSpace,
.Sdwa,
.Wavefrontsize64,
.SdwaSdst,
.FlatInstOffsets,
.ScalarStores,
.Gfx7Gfx8Gfx9Insts,
.R128A16,
.Dpp,
.Localmemorysize65536,
.Vop3p,
.BitInsts16,
.VgprIndexMode,
.Gfx8Insts,
.Inv2piInlineImm,
.Gfx9Insts,
.ScalarFlatScratchInsts,
.FlatGlobalInsts,
.FlatScratchInsts,
.Fp64,
.FastFmaf,
}),
FeatureInfo(@This()).create(.Gfx9Insts, "gfx9-insts", "Additional instructions for GFX9+", "gfx9-insts"),
FeatureInfo(@This()).createWithSubfeatures(.Gfx10, "gfx10", "GFX10 GPU generation", "gfx10", &[_]@This() {
.Vscnt,
.ApertureRegs,
.Gfx10Insts,
.IntClampInsts,
.PkFmacF16Inst,
.SdwaOmod,
.SdwaScalar,
.AddNoCarryInsts,
.Movrel,
.SMemrealtime,
.NoSdstCmpx,
.CiInsts,
.FlatAddressSpace,
.Sdwa,
.NoSramEccSupport,
.SdwaSdst,
.FlatInstOffsets,
.RegisterBanking,
.Dpp,
.Localmemorysize65536,
.Vop3p,
.BitInsts16,
.Dpp8,
.Gfx8Insts,
.Inv2piInlineImm,
.Gfx9Insts,
.FmaMixInsts,
.MimgR128,
.Vop3Literal,
.FlatGlobalInsts,
.FlatScratchInsts,
.Fp64,
.FastFmaf,
.NoDataDepHazard,
}),
FeatureInfo(@This()).create(.Gfx10Insts, "gfx10-insts", "Additional instructions for GFX10+", "gfx10-insts"),
FeatureInfo(@This()).create(.InstFwdPrefetchBug, "inst-fwd-prefetch-bug", "S_INST_PREFETCH instruction causes shader to hang", "inst-fwd-prefetch-bug"),
FeatureInfo(@This()).create(.IntClampInsts, "int-clamp-insts", "Support clamp for integer destination", "int-clamp-insts"),
FeatureInfo(@This()).create(.Inv2piInlineImm, "inv-2pi-inline-imm", "Has 1 / (2 * pi) as inline immediate", "inv-2pi-inline-imm"),
FeatureInfo(@This()).create(.Ldsbankcount16, "ldsbankcount16", "The number of LDS banks per compute unit.", "ldsbankcount16"),
FeatureInfo(@This()).create(.Ldsbankcount32, "ldsbankcount32", "The number of LDS banks per compute unit.", "ldsbankcount32"),
FeatureInfo(@This()).create(.LdsBranchVmemWarHazard, "lds-branch-vmem-war-hazard", "Switching between LDS and VMEM-tex not waiting VM_VSRC=0", "lds-branch-vmem-war-hazard"),
FeatureInfo(@This()).create(.LdsMisalignedBug, "lds-misaligned-bug", "Some GFX10 bug with misaligned multi-dword LDS access in WGP mode", "lds-misaligned-bug"),
FeatureInfo(@This()).create(.Localmemorysize0, "localmemorysize0", "The size of local memory in bytes", "localmemorysize0"),
FeatureInfo(@This()).create(.Localmemorysize32768, "localmemorysize32768", "The size of local memory in bytes", "localmemorysize32768"),
FeatureInfo(@This()).create(.Localmemorysize65536, "localmemorysize65536", "The size of local memory in bytes", "localmemorysize65536"),
FeatureInfo(@This()).create(.MaiInsts, "mai-insts", "Has mAI instructions", "mai-insts"),
FeatureInfo(@This()).create(.MfmaInlineLiteralBug, "mfma-inline-literal-bug", "MFMA cannot use inline literal as SrcC", "mfma-inline-literal-bug"),
FeatureInfo(@This()).create(.MimgR128, "mimg-r128", "Support 128-bit texture resources", "mimg-r128"),
FeatureInfo(@This()).create(.MadMixInsts, "mad-mix-insts", "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions", "mad-mix-insts"),
FeatureInfo(@This()).create(.MaxPrivateElementSize4, "max-private-element-size-4", "Maximum private access size may be 4", "max-private-element-size-4"),
FeatureInfo(@This()).create(.MaxPrivateElementSize8, "max-private-element-size-8", "Maximum private access size may be 8", "max-private-element-size-8"),
FeatureInfo(@This()).create(.MaxPrivateElementSize16, "max-private-element-size-16", "Maximum private access size may be 16", "max-private-element-size-16"),
FeatureInfo(@This()).create(.Movrel, "movrel", "Has v_movrel*_b32 instructions", "movrel"),
FeatureInfo(@This()).create(.NsaEncoding, "nsa-encoding", "Support NSA encoding for image instructions", "nsa-encoding"),
FeatureInfo(@This()).create(.NsaToVmemBug, "nsa-to-vmem-bug", "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero", "nsa-to-vmem-bug"),
FeatureInfo(@This()).create(.NoDataDepHazard, "no-data-dep-hazard", "Does not need SW waitstates", "no-data-dep-hazard"),
FeatureInfo(@This()).create(.NoSdstCmpx, "no-sdst-cmpx", "V_CMPX does not write VCC/SGPR in addition to EXEC", "no-sdst-cmpx"),
FeatureInfo(@This()).create(.Offset3fBug, "offset-3f-bug", "Branch offset of 3f hardware bug", "offset-3f-bug"),
FeatureInfo(@This()).create(.PkFmacF16Inst, "pk-fmac-f16-inst", "Has v_pk_fmac_f16 instruction", "pk-fmac-f16-inst"),
FeatureInfo(@This()).create(.PromoteAlloca, "promote-alloca", "Enable promote alloca pass", "promote-alloca"),
FeatureInfo(@This()).create(.R128A16, "r128-a16", "Support 16 bit coordindates/gradients/lod/clamp/mip types on gfx9", "r128-a16"),
FeatureInfo(@This()).create(.RegisterBanking, "register-banking", "Has register banking", "register-banking"),
FeatureInfo(@This()).create(.Sdwa, "sdwa", "Support SDWA (Sub-DWORD Addressing) extension", "sdwa"),
FeatureInfo(@This()).create(.SdwaMav, "sdwa-mav", "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension", "sdwa-mav"),
FeatureInfo(@This()).create(.SdwaOmod, "sdwa-omod", "Support OMod with SDWA (Sub-DWORD Addressing) extension", "sdwa-omod"),
FeatureInfo(@This()).create(.SdwaOutModsVopc, "sdwa-out-mods-vopc", "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension", "sdwa-out-mods-vopc"),
FeatureInfo(@This()).create(.SdwaScalar, "sdwa-scalar", "Support scalar register with SDWA (Sub-DWORD Addressing) extension", "sdwa-scalar"),
FeatureInfo(@This()).create(.SdwaSdst, "sdwa-sdst", "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension", "sdwa-sdst"),
FeatureInfo(@This()).create(.SgprInitBug, "sgpr-init-bug", "VI SGPR initialization bug requiring a fixed SGPR allocation size", "sgpr-init-bug"),
FeatureInfo(@This()).create(.SmemToVectorWriteHazard, "smem-to-vector-write-hazard", "s_load_dword followed by v_cmp page faults", "smem-to-vector-write-hazard"),
FeatureInfo(@This()).create(.SMemrealtime, "s-memrealtime", "Has s_memrealtime instruction", "s-memrealtime"),
FeatureInfo(@This()).create(.SramEcc, "sram-ecc", "Enable SRAM ECC", "sram-ecc"),
FeatureInfo(@This()).create(.ScalarAtomics, "scalar-atomics", "Has atomic scalar memory instructions", "scalar-atomics"),
FeatureInfo(@This()).create(.ScalarFlatScratchInsts, "scalar-flat-scratch-insts", "Have s_scratch_* flat memory instructions", "scalar-flat-scratch-insts"),
FeatureInfo(@This()).create(.ScalarStores, "scalar-stores", "Has store scalar memory instructions", "scalar-stores"),
FeatureInfo(@This()).createWithSubfeatures(.SeaIslands, "sea-islands", "SEA_ISLANDS GPU generation", "sea-islands", &[_]@This() {
.Movrel,
.Gfx7Gfx8Gfx9Insts,
.Fp64,
.TrigReducedRange,
.CiInsts,
.FlatAddressSpace,
.Localmemorysize65536,
.Wavefrontsize64,
.NoSramEccSupport,
.MimgR128,
}),
FeatureInfo(@This()).createWithSubfeatures(.SouthernIslands, "southern-islands", "SOUTHERN_ISLANDS GPU generation", "southern-islands", &[_]@This() {
.Movrel,
.MimgR128,
.Fp64,
.TrigReducedRange,
.NoXnackSupport,
.Wavefrontsize64,
.NoSramEccSupport,
.Ldsbankcount32,
.Localmemorysize32768,
}),
FeatureInfo(@This()).create(.TrapHandler, "trap-handler", "Trap handler support", "trap-handler"),
FeatureInfo(@This()).create(.TrigReducedRange, "trig-reduced-range", "Requires use of fract on arguments to trig instructions", "trig-reduced-range"),
FeatureInfo(@This()).create(.UnalignedBufferAccess, "unaligned-buffer-access", "Support unaligned global loads and stores", "unaligned-buffer-access"),
FeatureInfo(@This()).create(.UnalignedScratchAccess, "unaligned-scratch-access", "Support unaligned scratch loads and stores", "unaligned-scratch-access"),
FeatureInfo(@This()).create(.UnpackedD16Vmem, "unpacked-d16-vmem", "Has unpacked d16 vmem instructions", "unpacked-d16-vmem"),
FeatureInfo(@This()).create(.VgprIndexMode, "vgpr-index-mode", "Has VGPR mode register indexing", "vgpr-index-mode"),
FeatureInfo(@This()).create(.VmemToScalarWriteHazard, "vmem-to-scalar-write-hazard", "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution.", "vmem-to-scalar-write-hazard"),
FeatureInfo(@This()).create(.Vop3Literal, "vop3-literal", "Can use one literal in VOP3", "vop3-literal"),
FeatureInfo(@This()).create(.Vop3p, "vop3p", "Has VOP3P packed instructions", "vop3p"),
FeatureInfo(@This()).create(.VcmpxExecWarHazard, "vcmpx-exec-war-hazard", "V_CMPX WAR hazard on EXEC (V_CMPX issue ONLY)", "vcmpx-exec-war-hazard"),
FeatureInfo(@This()).create(.VcmpxPermlaneHazard, "vcmpx-permlane-hazard", "TODO: describe me", "vcmpx-permlane-hazard"),
FeatureInfo(@This()).createWithSubfeatures(.VolcanicIslands, "volcanic-islands", "VOLCANIC_ISLANDS GPU generation", "volcanic-islands", &[_]@This() {
.IntClampInsts,
.SdwaMav,
.Movrel,
.SMemrealtime,
.Gcn3Encoding,
.TrigReducedRange,
.CiInsts,
.FlatAddressSpace,
.Sdwa,
.Wavefrontsize64,
.NoSramEccSupport,
.ScalarStores,
.Gfx7Gfx8Gfx9Insts,
.Dpp,
.Localmemorysize65536,
.BitInsts16,
.VgprIndexMode,
.Gfx8Insts,
.Inv2piInlineImm,
.MimgR128,
.SdwaOutModsVopc,
.Fp64,
}),
FeatureInfo(@This()).create(.Vscnt, "vscnt", "Has separate store vscnt counter", "vscnt"),
FeatureInfo(@This()).create(.Wavefrontsize16, "wavefrontsize16", "The number of threads per wavefront", "wavefrontsize16"),
FeatureInfo(@This()).create(.Wavefrontsize32, "wavefrontsize32", "The number of threads per wavefront", "wavefrontsize32"),
FeatureInfo(@This()).create(.Wavefrontsize64, "wavefrontsize64", "The number of threads per wavefront", "wavefrontsize64"),
FeatureInfo(@This()).create(.Xnack, "xnack", "Enable XNACK support", "xnack"),
FeatureInfo(@This()).create(.HalfRate64Ops, "half-rate-64-ops", "Most fp64 instructions are half rate instead of quarter", "half-rate-64-ops"),
};
};

818
lib/std/target/feature/ArmFeature.zig
View File

@@ -1,818 +0,0 @@
const FeatureInfo = @import("std").target.feature.FeatureInfo;
pub const ArmFeature = enum {
Armv2,
Armv2a,
Armv3,
Armv3m,
Armv4,
Armv4t,
Armv5t,
Armv5te,
Armv5tej,
Armv6,
Armv6j,
Armv6k,
Armv6kz,
Armv6M,
Armv6sM,
Armv6t2,
Armv7A,
Armv7eM,
Armv7k,
Armv7M,
Armv7R,
Armv7s,
Armv7ve,
Armv8A,
Armv8Mbase,
Armv8Mmain,
Armv8R,
Armv81A,
Armv81Mmain,
Armv82A,
Armv83A,
Armv84A,
Armv85A,
Msecext8,
Aclass,
Aes,
AcquireRelease,
AvoidMovsShop,
AvoidPartialCpsr,
Crc,
CheapPredicableCpsr,
VldnAlign,
Crypto,
D32,
Db,
Dfb,
Dsp,
DontWidenVmovs,
Dotprod,
ExecuteOnly,
ExpandFpMlx,
Fp16,
Fp16fml,
Fp64,
Fpao,
FpArmv8,
FpArmv8d16,
FpArmv8d16sp,
FpArmv8sp,
Fpregs,
Fpregs16,
Fpregs64,
Fullfp16,
FuseAes,
FuseLiterals,
HwdivArm,
Hwdiv,
NoBranchPredictor,
RetAddrStack,
Slowfpvmlx,
VmlxHazards,
Lob,
LongCalls,
Mclass,
Mp,
Mve1beat,
Mve2beat,
Mve4beat,
MuxedUnits,
Neon,
Neonfp,
NeonFpmovs,
NaclTrap,
Noarm,
NoMovt,
NoNegImmediates,
DisablePostraScheduler,
NonpipelinedVfp,
Perfmon,
Bit32,
PreferIshst,
LoopAlign,
PreferVmovsr,
ProfUnpr,
Ras,
Rclass,
ReadTpHard,
ReserveR9,
Sb,
Sha2,
SlowFpBrcc,
SlowLoadDSubreg,
SlowOddReg,
SlowVdup32,
SlowVgetlni32,
SplatVfpNeon,
StrictAlign,
Thumb2,
Trustzone,
UseAa,
UseMisched,
WideStrideVfp,
V7clrex,
Vfp2,
Vfp2sp,
Vfp3,
Vfp3d16,
Vfp3d16sp,
Vfp3sp,
Vfp4,
Vfp4d16,
Vfp4d16sp,
Vfp4sp,
VmlxForwarding,
Virtualization,
Zcz,
Mvefp,
Mve,
V4t,
V5te,
V5t,
V6k,
V6m,
V6,
V6t2,
V7,
V8m,
V8mmain,
V8,
V81mmain,
V81a,
V82a,
V83a,
V84a,
V85a,
Iwmmxt,
Iwmmxt2,
SoftFloat,
ThumbMode,
A5,
A7,
A8,
A9,
A12,
A15,
A17,
A32,
A35,
A53,
A55,
A57,
A72,
A73,
A75,
A76,
Exynos,
Krait,
Kryo,
M3,
R4,
R5,
R7,
R52,
Swift,
Xscale,
pub fn getInfo(self: @This()) FeatureInfo(@This()) {
return feature_infos[@enumToInt(self)];
}
pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
FeatureInfo(@This()).create(.Armv2, "armv2", "ARMv2 architecture", "armv2"),
FeatureInfo(@This()).create(.Armv2a, "armv2a", "ARMv2a architecture", "armv2a"),
FeatureInfo(@This()).create(.Armv3, "armv3", "ARMv3 architecture", "armv3"),
FeatureInfo(@This()).create(.Armv3m, "armv3m", "ARMv3m architecture", "armv3m"),
FeatureInfo(@This()).create(.Armv4, "armv4", "ARMv4 architecture", "armv4"),
FeatureInfo(@This()).createWithSubfeatures(.Armv4t, "armv4t", "ARMv4t architecture", "armv4t", &[_]@This() {
.V4t,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv5t, "armv5t", "ARMv5t architecture", "armv5t", &[_]@This() {
.V4t,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv5te, "armv5te", "ARMv5te architecture", "armv5te", &[_]@This() {
.V4t,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv5tej, "armv5tej", "ARMv5tej architecture", "armv5tej", &[_]@This() {
.V4t,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv6, "armv6", "ARMv6 architecture", "armv6", &[_]@This() {
.V4t,
.Dsp,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv6j, "armv6j", "ARMv7a architecture", "armv6j", &[_]@This() {
.V4t,
.Dsp,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv6k, "armv6k", "ARMv6k architecture", "armv6k", &[_]@This() {
.V4t,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv6kz, "armv6kz", "ARMv6kz architecture", "armv6kz", &[_]@This() {
.V4t,
.Trustzone,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv6M, "armv6-m", "ARMv6m architecture", "armv6-m", &[_]@This() {
.V4t,
.ThumbMode,
.Db,
.StrictAlign,
.Mclass,
.Noarm,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv6sM, "armv6s-m", "ARMv6sm architecture", "armv6s-m", &[_]@This() {
.V4t,
.ThumbMode,
.Db,
.StrictAlign,
.Mclass,
.Noarm,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv6t2, "armv6t2", "ARMv6t2 architecture", "armv6t2", &[_]@This() {
.V4t,
.Thumb2,
.Dsp,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv7A, "armv7-a", "ARMv7a architecture", "armv7-a", &[_]@This() {
.Perfmon,
.V4t,
.D32,
.Fpregs,
.V7clrex,
.Dsp,
.Thumb2,
.Db,
.Aclass,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv7eM, "armv7e-m", "ARMv7em architecture", "armv7e-m", &[_]@This() {
.Perfmon,
.V4t,
.ThumbMode,
.V7clrex,
.Dsp,
.Thumb2,
.Db,
.Mclass,
.Noarm,
.Hwdiv,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv7k, "armv7k", "ARMv7a architecture", "armv7k", &[_]@This() {
.Perfmon,
.V4t,
.D32,
.Fpregs,
.V7clrex,
.Dsp,
.Thumb2,
.Db,
.Aclass,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv7M, "armv7-m", "ARMv7m architecture", "armv7-m", &[_]@This() {
.Perfmon,
.V4t,
.ThumbMode,
.V7clrex,
.Thumb2,
.Db,
.Mclass,
.Noarm,
.Hwdiv,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv7R, "armv7-r", "ARMv7r architecture", "armv7-r", &[_]@This() {
.Perfmon,
.V4t,
.V7clrex,
.Dsp,
.Thumb2,
.Db,
.Hwdiv,
.Rclass,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv7s, "armv7s", "ARMv7a architecture", "armv7s", &[_]@This() {
.Perfmon,
.V4t,
.D32,
.Fpregs,
.V7clrex,
.Dsp,
.Thumb2,
.Db,
.Aclass,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv7ve, "armv7ve", "ARMv7ve architecture", "armv7ve", &[_]@This() {
.HwdivArm,
.Perfmon,
.D32,
.Mp,
.Fpregs,
.V4t,
.V7clrex,
.Dsp,
.Thumb2,
.Db,
.Aclass,
.Hwdiv,
.Trustzone,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv8A, "armv8-a", "ARMv8a architecture", "armv8-a", &[_]@This() {
.HwdivArm,
.Perfmon,
.D32,
.Fpregs,
.Crc,
.Mp,
.Fp16,
.Dsp,
.V4t,
.V7clrex,
.Db,
.Aclass,
.Thumb2,
.AcquireRelease,
.Hwdiv,
.Trustzone,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv8Mbase, "armv8-m.base", "ARMv8mBaseline architecture", "armv8-m.base", &[_]@This() {
.V4t,
.ThumbMode,
.Msecext8,
.V7clrex,
.Db,
.StrictAlign,
.Mclass,
.Noarm,
.AcquireRelease,
.Hwdiv,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv8Mmain, "armv8-m.main", "ARMv8mMainline architecture", "armv8-m.main", &[_]@This() {
.Perfmon,
.V4t,
.ThumbMode,
.Msecext8,
.V7clrex,
.Thumb2,
.Db,
.Mclass,
.Noarm,
.AcquireRelease,
.Hwdiv,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv8R, "armv8-r", "ARMv8r architecture", "armv8-r", &[_]@This() {
.HwdivArm,
.Perfmon,
.D32,
.Crc,
.Fpregs,
.Mp,
.Dfb,
.Dsp,
.Fp16,
.V4t,
.Db,
.V7clrex,
.Thumb2,
.AcquireRelease,
.Hwdiv,
.Rclass,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv81A, "armv8.1-a", "ARMv81a architecture", "armv8.1-a", &[_]@This() {
.HwdivArm,
.Perfmon,
.D32,
.Fpregs,
.Crc,
.Mp,
.Fp16,
.Dsp,
.V4t,
.V7clrex,
.Db,
.Aclass,
.Thumb2,
.AcquireRelease,
.Hwdiv,
.Trustzone,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv81Mmain, "armv8.1-m.main", "ARMv81mMainline architecture", "armv8.1-m.main", &[_]@This() {
.Perfmon,
.V4t,
.ThumbMode,
.Msecext8,
.V7clrex,
.Thumb2,
.Db,
.Ras,
.Mclass,
.Noarm,
.AcquireRelease,
.Hwdiv,
.Lob,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv82A, "armv8.2-a", "ARMv82a architecture", "armv8.2-a", &[_]@This() {
.HwdivArm,
.Perfmon,
.D32,
.Fpregs,
.Crc,
.Mp,
.Fp16,
.Dsp,
.V4t,
.V7clrex,
.Db,
.Aclass,
.Thumb2,
.Ras,
.AcquireRelease,
.Hwdiv,
.Trustzone,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv83A, "armv8.3-a", "ARMv83a architecture", "armv8.3-a", &[_]@This() {
.HwdivArm,
.Perfmon,
.D32,
.Fpregs,
.Crc,
.Mp,
.Fp16,
.Dsp,
.V4t,
.V7clrex,
.Db,
.Aclass,
.Thumb2,
.Ras,
.AcquireRelease,
.Hwdiv,
.Trustzone,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv84A, "armv8.4-a", "ARMv84a architecture", "armv8.4-a", &[_]@This() {
.HwdivArm,
.Perfmon,
.D32,
.Fpregs,
.Crc,
.Mp,
.Fp16,
.Dsp,
.V4t,
.V7clrex,
.Db,
.Aclass,
.Thumb2,
.Ras,
.AcquireRelease,
.Hwdiv,
.Trustzone,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv85A, "armv8.5-a", "ARMv85a architecture", "armv8.5-a", &[_]@This() {
.HwdivArm,
.Perfmon,
.D32,
.Fpregs,
.Crc,
.Mp,
.Fp16,
.Dsp,
.V4t,
.V7clrex,
.Db,
.Aclass,
.Thumb2,
.Ras,
.Sb,
.AcquireRelease,
.Hwdiv,
.Trustzone,
}),
FeatureInfo(@This()).create(.Msecext8, "8msecext", "Enable support for ARMv8-M Security Extensions", "8msecext"),
FeatureInfo(@This()).create(.Aclass, "aclass", "Is application profile ('A' series)", "aclass"),
FeatureInfo(@This()).createWithSubfeatures(.Aes, "aes", "Enable AES support", "aes", &[_]@This() {
.D32,
.Fpregs,
}),
FeatureInfo(@This()).create(.AcquireRelease, "acquire-release", "Has v8 acquire/release (lda/ldaex etc) instructions", "acquire-release"),
FeatureInfo(@This()).create(.AvoidMovsShop, "avoid-movs-shop", "Avoid movs instructions with shifter operand", "avoid-movs-shop"),
FeatureInfo(@This()).create(.AvoidPartialCpsr, "avoid-partial-cpsr", "Avoid CPSR partial update for OOO execution", "avoid-partial-cpsr"),
FeatureInfo(@This()).create(.Crc, "crc", "Enable support for CRC instructions", "crc"),
FeatureInfo(@This()).create(.CheapPredicableCpsr, "cheap-predicable-cpsr", "Disable +1 predication cost for instructions updating CPSR", "cheap-predicable-cpsr"),
FeatureInfo(@This()).create(.VldnAlign, "vldn-align", "Check for VLDn unaligned access", "vldn-align"),
FeatureInfo(@This()).createWithSubfeatures(.Crypto, "crypto", "Enable support for Cryptography extensions", "crypto", &[_]@This() {
.D32,
.Fpregs,
}),
FeatureInfo(@This()).create(.D32, "d32", "Extend FP to 32 double registers", "d32"),
FeatureInfo(@This()).create(.Db, "db", "Has data barrier (dmb/dsb) instructions", "db"),
FeatureInfo(@This()).create(.Dfb, "dfb", "Has full data barrier (dfb) instruction", "dfb"),
FeatureInfo(@This()).create(.Dsp, "dsp", "Supports DSP instructions in ARM and/or Thumb2", "dsp"),
FeatureInfo(@This()).create(.DontWidenVmovs, "dont-widen-vmovs", "Don't widen VMOVS to VMOVD", "dont-widen-vmovs"),
FeatureInfo(@This()).createWithSubfeatures(.Dotprod, "dotprod", "Enable support for dot product instructions", "dotprod", &[_]@This() {
.D32,
.Fpregs,
}),
FeatureInfo(@This()).create(.ExecuteOnly, "execute-only", "Enable the generation of execute only code.", "execute-only"),
FeatureInfo(@This()).create(.ExpandFpMlx, "expand-fp-mlx", "Expand VFP/NEON MLA/MLS instructions", "expand-fp-mlx"),
FeatureInfo(@This()).create(.Fp16, "fp16", "Enable half-precision floating point", "fp16"),
FeatureInfo(@This()).createWithSubfeatures(.Fp16fml, "fp16fml", "Enable full half-precision floating point fml instructions", "fp16fml", &[_]@This() {
.Fpregs,
.Fp16,
}),
FeatureInfo(@This()).createWithSubfeatures(.Fp64, "fp64", "Floating point unit supports double precision", "fp64", &[_]@This() {
.Fpregs,
}),
FeatureInfo(@This()).create(.Fpao, "fpao", "Enable fast computation of positive address offsets", "fpao"),
FeatureInfo(@This()).createWithSubfeatures(.FpArmv8, "fp-armv8", "Enable ARMv8 FP", "fp-armv8", &[_]@This() {
.D32,
.Fpregs,
.Fp16,
}),
FeatureInfo(@This()).createWithSubfeatures(.FpArmv8d16, "fp-armv8d16", "Enable ARMv8 FP with only 16 d-registers", "fp-armv8d16", &[_]@This() {
.Fpregs,
.Fp16,
}),
FeatureInfo(@This()).createWithSubfeatures(.FpArmv8d16sp, "fp-armv8d16sp", "Enable ARMv8 FP with only 16 d-registers and no double precision", "fp-armv8d16sp", &[_]@This() {
.Fpregs,
.Fp16,
}),
FeatureInfo(@This()).createWithSubfeatures(.FpArmv8sp, "fp-armv8sp", "Enable ARMv8 FP with no double precision", "fp-armv8sp", &[_]@This() {
.D32,
.Fpregs,
.Fp16,
}),
FeatureInfo(@This()).create(.Fpregs, "fpregs", "Enable FP registers", "fpregs"),
FeatureInfo(@This()).createWithSubfeatures(.Fpregs16, "fpregs16", "Enable 16-bit FP registers", "fpregs16", &[_]@This() {
.Fpregs,
}),
FeatureInfo(@This()).createWithSubfeatures(.Fpregs64, "fpregs64", "Enable 64-bit FP registers", "fpregs64", &[_]@This() {
.Fpregs,
}),
FeatureInfo(@This()).createWithSubfeatures(.Fullfp16, "fullfp16", "Enable full half-precision floating point", "fullfp16", &[_]@This() {
.Fpregs,
.Fp16,
}),
FeatureInfo(@This()).create(.FuseAes, "fuse-aes", "CPU fuses AES crypto operations", "fuse-aes"),
FeatureInfo(@This()).create(.FuseLiterals, "fuse-literals", "CPU fuses literal generation operations", "fuse-literals"),
FeatureInfo(@This()).create(.HwdivArm, "hwdiv-arm", "Enable divide instructions in ARM mode", "hwdiv-arm"),
FeatureInfo(@This()).create(.Hwdiv, "hwdiv", "Enable divide instructions in Thumb", "hwdiv"),
FeatureInfo(@This()).create(.NoBranchPredictor, "no-branch-predictor", "Has no branch predictor", "no-branch-predictor"),
FeatureInfo(@This()).create(.RetAddrStack, "ret-addr-stack", "Has return address stack", "ret-addr-stack"),
FeatureInfo(@This()).create(.Slowfpvmlx, "slowfpvmlx", "Disable VFP / NEON MAC instructions", "slowfpvmlx"),
FeatureInfo(@This()).create(.VmlxHazards, "vmlx-hazards", "Has VMLx hazards", "vmlx-hazards"),
FeatureInfo(@This()).create(.Lob, "lob", "Enable Low Overhead Branch extensions", "lob"),
FeatureInfo(@This()).create(.LongCalls, "long-calls", "Generate calls via indirect call instructions", "long-calls"),
FeatureInfo(@This()).create(.Mclass, "mclass", "Is microcontroller profile ('M' series)", "mclass"),
FeatureInfo(@This()).create(.Mp, "mp", "Supports Multiprocessing extension", "mp"),
FeatureInfo(@This()).create(.Mve1beat, "mve1beat", "Model MVE instructions as a 1 beat per tick architecture", "mve1beat"),
FeatureInfo(@This()).create(.Mve2beat, "mve2beat", "Model MVE instructions as a 2 beats per tick architecture", "mve2beat"),
FeatureInfo(@This()).create(.Mve4beat, "mve4beat", "Model MVE instructions as a 4 beats per tick architecture", "mve4beat"),
FeatureInfo(@This()).create(.MuxedUnits, "muxed-units", "Has muxed AGU and NEON/FPU", "muxed-units"),
FeatureInfo(@This()).createWithSubfeatures(.Neon, "neon", "Enable NEON instructions", "neon", &[_]@This() {
.D32,
.Fpregs,
}),
FeatureInfo(@This()).create(.Neonfp, "neonfp", "Use NEON for single precision FP", "neonfp"),
FeatureInfo(@This()).create(.NeonFpmovs, "neon-fpmovs", "Convert VMOVSR, VMOVRS, VMOVS to NEON", "neon-fpmovs"),
FeatureInfo(@This()).create(.NaclTrap, "nacl-trap", "NaCl trap", "nacl-trap"),
FeatureInfo(@This()).create(.Noarm, "noarm", "Does not support ARM mode execution", "noarm"),
FeatureInfo(@This()).create(.NoMovt, "no-movt", "Don't use movt/movw pairs for 32-bit imms", "no-movt"),
FeatureInfo(@This()).create(.NoNegImmediates, "no-neg-immediates", "Convert immediates and instructions to their negated or complemented equivalent when the immediate does not fit in the encoding.", "no-neg-immediates"),
FeatureInfo(@This()).create(.DisablePostraScheduler, "disable-postra-scheduler", "Don't schedule again after register allocation", "disable-postra-scheduler"),
FeatureInfo(@This()).create(.NonpipelinedVfp, "nonpipelined-vfp", "VFP instructions are not pipelined", "nonpipelined-vfp"),
FeatureInfo(@This()).create(.Perfmon, "perfmon", "Enable support for Performance Monitor extensions", "perfmon"),
FeatureInfo(@This()).create(.Bit32, "32bit", "Prefer 32-bit Thumb instrs", "32bit"),
FeatureInfo(@This()).create(.PreferIshst, "prefer-ishst", "Prefer ISHST barriers", "prefer-ishst"),
FeatureInfo(@This()).create(.LoopAlign, "loop-align", "Prefer 32-bit alignment for loops", "loop-align"),
FeatureInfo(@This()).create(.PreferVmovsr, "prefer-vmovsr", "Prefer VMOVSR", "prefer-vmovsr"),
FeatureInfo(@This()).create(.ProfUnpr, "prof-unpr", "Is profitable to unpredicate", "prof-unpr"),
FeatureInfo(@This()).create(.Ras, "ras", "Enable Reliability, Availability and Serviceability extensions", "ras"),
FeatureInfo(@This()).create(.Rclass, "rclass", "Is realtime profile ('R' series)", "rclass"),
FeatureInfo(@This()).create(.ReadTpHard, "read-tp-hard", "Reading thread pointer from register", "read-tp-hard"),
FeatureInfo(@This()).create(.ReserveR9, "reserve-r9", "Reserve R9, making it unavailable as GPR", "reserve-r9"),
FeatureInfo(@This()).create(.Sb, "sb", "Enable v8.5a Speculation Barrier", "sb"),
FeatureInfo(@This()).createWithSubfeatures(.Sha2, "sha2", "Enable SHA1 and SHA256 support", "sha2", &[_]@This() {
.D32,
.Fpregs,
}),
FeatureInfo(@This()).create(.SlowFpBrcc, "slow-fp-brcc", "FP compare + branch is slow", "slow-fp-brcc"),
FeatureInfo(@This()).create(.SlowLoadDSubreg, "slow-load-D-subreg", "Loading into D subregs is slow", "slow-load-D-subreg"),
FeatureInfo(@This()).create(.SlowOddReg, "slow-odd-reg", "VLDM/VSTM starting with an odd register is slow", "slow-odd-reg"),
FeatureInfo(@This()).create(.SlowVdup32, "slow-vdup32", "Has slow VDUP32 - prefer VMOV", "slow-vdup32"),
FeatureInfo(@This()).create(.SlowVgetlni32, "slow-vgetlni32", "Has slow VGETLNi32 - prefer VMOV", "slow-vgetlni32"),
FeatureInfo(@This()).createWithSubfeatures(.SplatVfpNeon, "splat-vfp-neon", "Splat register from VFP to NEON", "splat-vfp-neon", &[_]@This() {
.DontWidenVmovs,
}),
FeatureInfo(@This()).create(.StrictAlign, "strict-align", "Disallow all unaligned memory access", "strict-align"),
FeatureInfo(@This()).create(.Thumb2, "thumb2", "Enable Thumb2 instructions", "thumb2"),
FeatureInfo(@This()).create(.Trustzone, "trustzone", "Enable support for TrustZone security extensions", "trustzone"),
FeatureInfo(@This()).create(.UseAa, "use-aa", "Use alias analysis during codegen", "use-aa"),
FeatureInfo(@This()).create(.UseMisched, "use-misched", "Use the MachineScheduler", "use-misched"),
FeatureInfo(@This()).create(.WideStrideVfp, "wide-stride-vfp", "Use a wide stride when allocating VFP registers", "wide-stride-vfp"),
FeatureInfo(@This()).create(.V7clrex, "v7clrex", "Has v7 clrex instruction", "v7clrex"),
FeatureInfo(@This()).createWithSubfeatures(.Vfp2, "vfp2", "Enable VFP2 instructions", "vfp2", &[_]@This() {
.Fpregs,
}),
FeatureInfo(@This()).createWithSubfeatures(.Vfp2sp, "vfp2sp", "Enable VFP2 instructions with no double precision", "vfp2sp", &[_]@This() {
.Fpregs,
}),
FeatureInfo(@This()).createWithSubfeatures(.Vfp3, "vfp3", "Enable VFP3 instructions", "vfp3", &[_]@This() {
.D32,
.Fpregs,
}),
FeatureInfo(@This()).createWithSubfeatures(.Vfp3d16, "vfp3d16", "Enable VFP3 instructions with only 16 d-registers", "vfp3d16", &[_]@This() {
.Fpregs,
}),
FeatureInfo(@This()).createWithSubfeatures(.Vfp3d16sp, "vfp3d16sp", "Enable VFP3 instructions with only 16 d-registers and no double precision", "vfp3d16sp", &[_]@This() {
.Fpregs,
}),
FeatureInfo(@This()).createWithSubfeatures(.Vfp3sp, "vfp3sp", "Enable VFP3 instructions with no double precision", "vfp3sp", &[_]@This() {
.D32,
.Fpregs,
}),
FeatureInfo(@This()).createWithSubfeatures(.Vfp4, "vfp4", "Enable VFP4 instructions", "vfp4", &[_]@This() {
.D32,
.Fpregs,
.Fp16,
}),
FeatureInfo(@This()).createWithSubfeatures(.Vfp4d16, "vfp4d16", "Enable VFP4 instructions with only 16 d-registers", "vfp4d16", &[_]@This() {
.Fpregs,
.Fp16,
}),
FeatureInfo(@This()).createWithSubfeatures(.Vfp4d16sp, "vfp4d16sp", "Enable VFP4 instructions with only 16 d-registers and no double precision", "vfp4d16sp", &[_]@This() {
.Fpregs,
.Fp16,
}),
FeatureInfo(@This()).createWithSubfeatures(.Vfp4sp, "vfp4sp", "Enable VFP4 instructions with no double precision", "vfp4sp", &[_]@This() {
.D32,
.Fpregs,
.Fp16,
}),
FeatureInfo(@This()).create(.VmlxForwarding, "vmlx-forwarding", "Has multiplier accumulator forwarding", "vmlx-forwarding"),
FeatureInfo(@This()).createWithSubfeatures(.Virtualization, "virtualization", "Supports Virtualization extension", "virtualization", &[_]@This() {
.HwdivArm,
.Hwdiv,
}),
FeatureInfo(@This()).create(.Zcz, "zcz", "Has zero-cycle zeroing instructions", "zcz"),
FeatureInfo(@This()).createWithSubfeatures(.Mvefp, "mve.fp", "Support M-Class Vector Extension with integer and floating ops", "mve.fp", &[_]@This() {
.Perfmon,
.V4t,
.Fpregs,
.V7clrex,
.Fp16,
.Dsp,
.Thumb2,
}),
FeatureInfo(@This()).createWithSubfeatures(.Mve, "mve", "Support M-Class Vector Extension with integer ops", "mve", &[_]@This() {
.Perfmon,
.V4t,
.Fpregs,
.V7clrex,
.Dsp,
.Thumb2,
}),
FeatureInfo(@This()).create(.V4t, "v4t", "Support ARM v4T instructions", "v4t"),
FeatureInfo(@This()).createWithSubfeatures(.V5te, "v5te", "Support ARM v5TE, v5TEj, and v5TExp instructions", "v5te", &[_]@This() {
.V4t,
}),
FeatureInfo(@This()).createWithSubfeatures(.V5t, "v5t", "Support ARM v5T instructions", "v5t", &[_]@This() {
.V4t,
}),
FeatureInfo(@This()).createWithSubfeatures(.V6k, "v6k", "Support ARM v6k instructions", "v6k", &[_]@This() {
.V4t,
}),
FeatureInfo(@This()).createWithSubfeatures(.V6m, "v6m", "Support ARM v6M instructions", "v6m", &[_]@This() {
.V4t,
}),
FeatureInfo(@This()).createWithSubfeatures(.V6, "v6", "Support ARM v6 instructions", "v6", &[_]@This() {
.V4t,
}),
FeatureInfo(@This()).createWithSubfeatures(.V6t2, "v6t2", "Support ARM v6t2 instructions", "v6t2", &[_]@This() {
.V4t,
.Thumb2,
}),
FeatureInfo(@This()).createWithSubfeatures(.V7, "v7", "Support ARM v7 instructions", "v7", &[_]@This() {
.Perfmon,
.Thumb2,
.V4t,
.V7clrex,
}),
FeatureInfo(@This()).createWithSubfeatures(.V8m, "v8m", "Support ARM v8M Baseline instructions", "v8m", &[_]@This() {
.V4t,
}),
FeatureInfo(@This()).createWithSubfeatures(.V8mmain, "v8m.main", "Support ARM v8M Mainline instructions", "v8m.main", &[_]@This() {
.Perfmon,
.Thumb2,
.V4t,
.V7clrex,
}),
FeatureInfo(@This()).createWithSubfeatures(.V8, "v8", "Support ARM v8 instructions", "v8", &[_]@This() {
.Perfmon,
.V4t,
.V7clrex,
.Thumb2,
.AcquireRelease,
}),
FeatureInfo(@This()).createWithSubfeatures(.V81mmain, "v8.1m.main", "Support ARM v8-1M Mainline instructions", "v8.1m.main", &[_]@This() {
.Perfmon,
.Thumb2,
.V4t,
.V7clrex,
}),
FeatureInfo(@This()).createWithSubfeatures(.V81a, "v8.1a", "Support ARM v8.1a instructions", "v8.1a", &[_]@This() {
.Perfmon,
.V4t,
.V7clrex,
.Thumb2,
.AcquireRelease,
}),
FeatureInfo(@This()).createWithSubfeatures(.V82a, "v8.2a", "Support ARM v8.2a instructions", "v8.2a", &[_]@This() {
.Perfmon,
.V4t,
.V7clrex,
.Thumb2,
.AcquireRelease,
}),
FeatureInfo(@This()).createWithSubfeatures(.V83a, "v8.3a", "Support ARM v8.3a instructions", "v8.3a", &[_]@This() {
.Perfmon,
.V4t,
.V7clrex,
.Thumb2,
.AcquireRelease,
}),
FeatureInfo(@This()).createWithSubfeatures(.V84a, "v8.4a", "Support ARM v8.4a instructions", "v8.4a", &[_]@This() {
.Perfmon,
.V4t,
.D32,
.Fpregs,
.V7clrex,
.Thumb2,
.AcquireRelease,
}),
FeatureInfo(@This()).createWithSubfeatures(.V85a, "v8.5a", "Support ARM v8.5a instructions", "v8.5a", &[_]@This() {
.Perfmon,
.V4t,
.D32,
.Fpregs,
.V7clrex,
.Thumb2,
.AcquireRelease,
.Sb,
}),
FeatureInfo(@This()).createWithSubfeatures(.Iwmmxt, "iwmmxt", "ARMv5te architecture", "iwmmxt", &[_]@This() {
.V4t,
}),
FeatureInfo(@This()).createWithSubfeatures(.Iwmmxt2, "iwmmxt2", "ARMv5te architecture", "iwmmxt2", &[_]@This() {
.V4t,
}),
FeatureInfo(@This()).create(.SoftFloat, "soft-float", "Use software floating point features.", "soft-float"),
FeatureInfo(@This()).create(.ThumbMode, "thumb-mode", "Thumb mode", "thumb-mode"),
FeatureInfo(@This()).create(.A5, "a5", "Cortex-A5 ARM processors", "a5"),
FeatureInfo(@This()).create(.A7, "a7", "Cortex-A7 ARM processors", "a7"),
FeatureInfo(@This()).create(.A8, "a8", "Cortex-A8 ARM processors", "a8"),
FeatureInfo(@This()).create(.A9, "a9", "Cortex-A9 ARM processors", "a9"),
FeatureInfo(@This()).create(.A12, "a12", "Cortex-A12 ARM processors", "a12"),
FeatureInfo(@This()).create(.A15, "a15", "Cortex-A15 ARM processors", "a15"),
FeatureInfo(@This()).create(.A17, "a17", "Cortex-A17 ARM processors", "a17"),
FeatureInfo(@This()).create(.A32, "a32", "Cortex-A32 ARM processors", "a32"),
FeatureInfo(@This()).create(.A35, "a35", "Cortex-A35 ARM processors", "a35"),
FeatureInfo(@This()).create(.A53, "a53", "Cortex-A53 ARM processors", "a53"),
FeatureInfo(@This()).create(.A55, "a55", "Cortex-A55 ARM processors", "a55"),
FeatureInfo(@This()).create(.A57, "a57", "Cortex-A57 ARM processors", "a57"),
FeatureInfo(@This()).create(.A72, "a72", "Cortex-A72 ARM processors", "a72"),
FeatureInfo(@This()).create(.A73, "a73", "Cortex-A73 ARM processors", "a73"),
FeatureInfo(@This()).create(.A75, "a75", "Cortex-A75 ARM processors", "a75"),
FeatureInfo(@This()).create(.A76, "a76", "Cortex-A76 ARM processors", "a76"),
FeatureInfo(@This()).createWithSubfeatures(.Exynos, "exynos", "Samsung Exynos processors", "exynos", &[_]@This() {
.HwdivArm,
.D32,
.Crc,
.Fpregs,
.RetAddrStack,
.SlowVgetlni32,
.WideStrideVfp,
.SlowVdup32,
.SlowFpBrcc,
.ProfUnpr,
.DontWidenVmovs,
.Zcz,
.Hwdiv,
.FuseAes,
.Slowfpvmlx,
.UseAa,
.FuseLiterals,
.ExpandFpMlx,
}),
FeatureInfo(@This()).create(.Krait, "krait", "Qualcomm Krait processors", "krait"),
FeatureInfo(@This()).create(.Kryo, "kryo", "Qualcomm Kryo processors", "kryo"),
FeatureInfo(@This()).create(.M3, "m3", "Cortex-M3 ARM processors", "m3"),
FeatureInfo(@This()).create(.R4, "r4", "Cortex-R4 ARM processors", "r4"),
FeatureInfo(@This()).create(.R5, "r5", "Cortex-R5 ARM processors", "r5"),
FeatureInfo(@This()).create(.R7, "r7", "Cortex-R7 ARM processors", "r7"),
FeatureInfo(@This()).create(.R52, "r52", "Cortex-R52 ARM processors", "r52"),
FeatureInfo(@This()).create(.Swift, "swift", "Swift ARM processors", "swift"),
FeatureInfo(@This()).createWithSubfeatures(.Xscale, "xscale", "ARMv5te architecture", "xscale", &[_]@This() {
.V4t,
}),
};
};

230
lib/std/target/feature/AvrFeature.zig
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@@ -1,230 +0,0 @@
const FeatureInfo = @import("std").target.feature.FeatureInfo;
pub const AvrFeature = enum {
Avr0,
Avr1,
Avr2,
Avr3,
Avr4,
Avr5,
Avr6,
Avr25,
Avr31,
Avr35,
Avr51,
Avrtiny,
Xmega,
Xmegau,
Addsubiw,
Break,
Des,
Eijmpcall,
Elpm,
Elpmx,
Ijmpcall,
Jmpcall,
Lpm,
Lpmx,
Movw,
Mul,
Rmw,
Spm,
Spmx,
Sram,
Special,
Smallstack,
Tinyencoding,
pub fn getInfo(self: @This()) FeatureInfo(@This()) {
return feature_infos[@enumToInt(self)];
}
pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
FeatureInfo(@This()).create(.Avr0, "avr0", "The device is a part of the avr0 family", "avr0"),
FeatureInfo(@This()).createWithSubfeatures(.Avr1, "avr1", "The device is a part of the avr1 family", "avr1", &[_]@This() {
.Avr0,
.Lpm,
}),
FeatureInfo(@This()).createWithSubfeatures(.Avr2, "avr2", "The device is a part of the avr2 family", "avr2", &[_]@This() {
.Lpm,
.Avr0,
.Sram,
.Addsubiw,
.Ijmpcall,
}),
FeatureInfo(@This()).createWithSubfeatures(.Avr3, "avr3", "The device is a part of the avr3 family", "avr3", &[_]@This() {
.Lpm,
.Avr0,
.Sram,
.Jmpcall,
.Addsubiw,
.Ijmpcall,
}),
FeatureInfo(@This()).createWithSubfeatures(.Avr4, "avr4", "The device is a part of the avr4 family", "avr4", &[_]@This() {
.Lpm,
.Movw,
.Spm,
.Avr0,
.Sram,
.Addsubiw,
.Mul,
.Lpmx,
.Ijmpcall,
.Break,
}),
FeatureInfo(@This()).createWithSubfeatures(.Avr5, "avr5", "The device is a part of the avr5 family", "avr5", &[_]@This() {
.Lpm,
.Movw,
.Spm,
.Avr0,
.Sram,
.Jmpcall,
.Addsubiw,
.Mul,
.Lpmx,
.Ijmpcall,
.Break,
}),
FeatureInfo(@This()).createWithSubfeatures(.Avr6, "avr6", "The device is a part of the avr6 family", "avr6", &[_]@This() {
.Lpm,
.Elpm,
.Movw,
.Elpmx,
.Spm,
.Avr0,
.Sram,
.Jmpcall,
.Addsubiw,
.Mul,
.Lpmx,
.Ijmpcall,
.Break,
}),
FeatureInfo(@This()).createWithSubfeatures(.Avr25, "avr25", "The device is a part of the avr25 family", "avr25", &[_]@This() {
.Lpm,
.Movw,
.Spm,
.Avr0,
.Sram,
.Addsubiw,
.Lpmx,
.Ijmpcall,
.Break,
}),
FeatureInfo(@This()).createWithSubfeatures(.Avr31, "avr31", "The device is a part of the avr31 family", "avr31", &[_]@This() {
.Lpm,
.Elpm,
.Avr0,
.Sram,
.Jmpcall,
.Addsubiw,
.Ijmpcall,
}),
FeatureInfo(@This()).createWithSubfeatures(.Avr35, "avr35", "The device is a part of the avr35 family", "avr35", &[_]@This() {
.Lpm,
.Movw,
.Spm,
.Avr0,
.Sram,
.Jmpcall,
.Addsubiw,
.Lpmx,
.Ijmpcall,
.Break,
}),
FeatureInfo(@This()).createWithSubfeatures(.Avr51, "avr51", "The device is a part of the avr51 family", "avr51", &[_]@This() {
.Lpm,
.Elpm,
.Movw,
.Elpmx,
.Spm,
.Avr0,
.Sram,
.Jmpcall,
.Addsubiw,
.Mul,
.Lpmx,
.Ijmpcall,
.Break,
}),
FeatureInfo(@This()).createWithSubfeatures(.Avrtiny, "avrtiny", "The device is a part of the avrtiny family", "avrtiny", &[_]@This() {
.Avr0,
.Sram,
.Break,
.Tinyencoding,
}),
FeatureInfo(@This()).createWithSubfeatures(.Xmega, "xmega", "The device is a part of the xmega family", "xmega", &[_]@This() {
.Lpm,
.Elpm,
.Movw,
.Elpmx,
.Spm,
.Avr0,
.Sram,
.Jmpcall,
.Eijmpcall,
.Spmx,
.Addsubiw,
.Mul,
.Lpmx,
.Des,
.Ijmpcall,
.Break,
}),
FeatureInfo(@This()).createWithSubfeatures(.Xmegau, "xmegau", "The device is a part of the xmegau family", "xmegau", &[_]@This() {
.Lpm,
.Elpm,
.Movw,
.Elpmx,
.Spm,
.Avr0,
.Sram,
.Jmpcall,
.Eijmpcall,
.Spmx,
.Addsubiw,
.Mul,
.Lpmx,
.Rmw,
.Des,
.Ijmpcall,
.Break,
}),
FeatureInfo(@This()).create(.Addsubiw, "addsubiw", "Enable 16-bit register-immediate addition and subtraction instructions", "addsubiw"),
FeatureInfo(@This()).create(.Break, "break", "The device supports the `BREAK` debugging instruction", "break"),
FeatureInfo(@This()).create(.Des, "des", "The device supports the `DES k` encryption instruction", "des"),
FeatureInfo(@This()).create(.Eijmpcall, "eijmpcall", "The device supports the `EIJMP`/`EICALL` instructions", "eijmpcall"),
FeatureInfo(@This()).create(.Elpm, "elpm", "The device supports the ELPM instruction", "elpm"),
FeatureInfo(@This()).create(.Elpmx, "elpmx", "The device supports the `ELPM Rd, Z[+]` instructions", "elpmx"),
FeatureInfo(@This()).create(.Ijmpcall, "ijmpcall", "The device supports `IJMP`/`ICALL`instructions", "ijmpcall"),
FeatureInfo(@This()).create(.Jmpcall, "jmpcall", "The device supports the `JMP` and `CALL` instructions", "jmpcall"),
FeatureInfo(@This()).create(.Lpm, "lpm", "The device supports the `LPM` instruction", "lpm"),
FeatureInfo(@This()).create(.Lpmx, "lpmx", "The device supports the `LPM Rd, Z[+]` instruction", "lpmx"),
FeatureInfo(@This()).create(.Movw, "movw", "The device supports the 16-bit MOVW instruction", "movw"),
FeatureInfo(@This()).create(.Mul, "mul", "The device supports the multiplication instructions", "mul"),
FeatureInfo(@This()).create(.Rmw, "rmw", "The device supports the read-write-modify instructions: XCH, LAS, LAC, LAT", "rmw"),
FeatureInfo(@This()).create(.Spm, "spm", "The device supports the `SPM` instruction", "spm"),
FeatureInfo(@This()).create(.Spmx, "spmx", "The device supports the `SPM Z+` instruction", "spmx"),
FeatureInfo(@This()).create(.Sram, "sram", "The device has random access memory", "sram"),
FeatureInfo(@This()).createWithSubfeatures(.Special, "special", "Enable use of the entire instruction set - used for debugging", "special", &[_]@This() {
.Lpm,
.Elpm,
.Elpmx,
.Movw,
.Spm,
.Eijmpcall,
.Spmx,
.Jmpcall,
.Sram,
.Addsubiw,
.Mul,
.Lpmx,
.Rmw,
.Des,
.Ijmpcall,
.Break,
}),
FeatureInfo(@This()).create(.Smallstack, "smallstack", "The device has an 8-bit stack pointer", "smallstack"),
FeatureInfo(@This()).create(.Tinyencoding, "tinyencoding", "The device has Tiny core specific instruction encodings", "tinyencoding"),
};
};

17
lib/std/target/feature/BpfFeature.zig
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@@ -1,17 +0,0 @@
const FeatureInfo = @import("std").target.feature.FeatureInfo;
pub const BpfFeature = enum {
Alu32,
Dummy,
Dwarfris,
pub fn getInfo(self: @This()) FeatureInfo(@This()) {
return feature_infos[@enumToInt(self)];
}
pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
FeatureInfo(@This()).create(.Alu32, "alu32", "Enable ALU32 instructions", "alu32"),
FeatureInfo(@This()).create(.Dummy, "dummy", "unused feature", "dummy"),
FeatureInfo(@This()).create(.Dwarfris, "dwarfris", "Disable MCAsmInfo DwarfUsesRelocationsAcrossSections", "dwarfris"),
};
};

76
lib/std/target/feature/HexagonFeature.zig
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@@ -1,76 +0,0 @@
const FeatureInfo = @import("std").target.feature.FeatureInfo;
pub const HexagonFeature = enum {
V5,
V55,
V60,
V62,
V65,
V66,
Hvx,
HvxLength64b,
HvxLength128b,
Hvxv60,
Hvxv62,
Hvxv65,
Hvxv66,
Zreg,
Duplex,
LongCalls,
Mem_noshuf,
Memops,
Nvj,
Nvs,
NoreturnStackElim,
Packets,
ReservedR19,
SmallData,
pub fn getInfo(self: @This()) FeatureInfo(@This()) {
return feature_infos[@enumToInt(self)];
}
pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
FeatureInfo(@This()).create(.V5, "v5", "Enable Hexagon V5 architecture", "v5"),
FeatureInfo(@This()).create(.V55, "v55", "Enable Hexagon V55 architecture", "v55"),
FeatureInfo(@This()).create(.V60, "v60", "Enable Hexagon V60 architecture", "v60"),
FeatureInfo(@This()).create(.V62, "v62", "Enable Hexagon V62 architecture", "v62"),
FeatureInfo(@This()).create(.V65, "v65", "Enable Hexagon V65 architecture", "v65"),
FeatureInfo(@This()).create(.V66, "v66", "Enable Hexagon V66 architecture", "v66"),
FeatureInfo(@This()).create(.Hvx, "hvx", "Hexagon HVX instructions", "hvx"),
FeatureInfo(@This()).createWithSubfeatures(.HvxLength64b, "hvx-length64b", "Hexagon HVX 64B instructions", "hvx-length64b", &[_]@This() {
.Hvx,
}),
FeatureInfo(@This()).createWithSubfeatures(.HvxLength128b, "hvx-length128b", "Hexagon HVX 128B instructions", "hvx-length128b", &[_]@This() {
.Hvx,
}),
FeatureInfo(@This()).createWithSubfeatures(.Hvxv60, "hvxv60", "Hexagon HVX instructions", "hvxv60", &[_]@This() {
.Hvx,
}),
FeatureInfo(@This()).createWithSubfeatures(.Hvxv62, "hvxv62", "Hexagon HVX instructions", "hvxv62", &[_]@This() {
.Hvx,
}),
FeatureInfo(@This()).createWithSubfeatures(.Hvxv65, "hvxv65", "Hexagon HVX instructions", "hvxv65", &[_]@This() {
.Hvx,
}),
FeatureInfo(@This()).createWithSubfeatures(.Hvxv66, "hvxv66", "Hexagon HVX instructions", "hvxv66", &[_]@This() {
.Hvx,
.Zreg,
}),
FeatureInfo(@This()).create(.Zreg, "zreg", "Hexagon ZReg extension instructions", "zreg"),
FeatureInfo(@This()).create(.Duplex, "duplex", "Enable generation of duplex instruction", "duplex"),
FeatureInfo(@This()).create(.LongCalls, "long-calls", "Use constant-extended calls", "long-calls"),
FeatureInfo(@This()).create(.Mem_noshuf, "mem_noshuf", "Supports mem_noshuf feature", "mem_noshuf"),
FeatureInfo(@This()).create(.Memops, "memops", "Use memop instructions", "memops"),
FeatureInfo(@This()).createWithSubfeatures(.Nvj, "nvj", "Support for new-value jumps", "nvj", &[_]@This() {
.Packets,
}),
FeatureInfo(@This()).createWithSubfeatures(.Nvs, "nvs", "Support for new-value stores", "nvs", &[_]@This() {
.Packets,
}),
FeatureInfo(@This()).create(.NoreturnStackElim, "noreturn-stack-elim", "Eliminate stack allocation in a noreturn function when possible", "noreturn-stack-elim"),
FeatureInfo(@This()).create(.Packets, "packets", "Support for instruction packets", "packets"),
FeatureInfo(@This()).create(.ReservedR19, "reserved-r19", "Reserve register R19", "reserved-r19"),
FeatureInfo(@This()).create(.SmallData, "small-data", "Allow GP-relative addressing of global variables", "small-data"),
};
};

238
lib/std/target/feature/MipsFeature.zig
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@@ -1,238 +0,0 @@
const FeatureInfo = @import("std").target.feature.FeatureInfo;
pub const MipsFeature = enum {
Abs2008,
Crc,
Cnmips,
Dsp,
Dspr2,
Dspr3,
Eva,
Fp64,
Fpxx,
Ginv,
Gp64,
LongCalls,
Msa,
Mt,
Nomadd4,
Micromips,
Mips1,
Mips2,
Mips3,
Mips3_32,
Mips3_32r2,
Mips4,
Mips4_32,
Mips4_32r2,
Mips5,
Mips5_32r2,
Mips16,
Mips32,
Mips32r2,
Mips32r3,
Mips32r5,
Mips32r6,
Mips64,
Mips64r2,
Mips64r3,
Mips64r5,
Mips64r6,
Nan2008,
Noabicalls,
Nooddspreg,
Ptr64,
SingleFloat,
SoftFloat,
Sym32,
UseIndirectJumpHazard,
UseTccInDiv,
Vfpu,
Virt,
Xgot,
P5600,
pub fn getInfo(self: @This()) FeatureInfo(@This()) {
return feature_infos[@enumToInt(self)];
}
pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
FeatureInfo(@This()).create(.Abs2008, "abs2008", "Disable IEEE 754-2008 abs.fmt mode", "abs2008"),
FeatureInfo(@This()).create(.Crc, "crc", "Mips R6 CRC ASE", "crc"),
FeatureInfo(@This()).createWithSubfeatures(.Cnmips, "cnmips", "Octeon cnMIPS Support", "cnmips", &[_]@This() {
.Mips5_32r2,
.Mips3_32r2,
.Mips4_32r2,
.Gp64,
.Fp64,
.Mips4_32,
.Mips1,
.Mips3_32,
}),
FeatureInfo(@This()).create(.Dsp, "dsp", "Mips DSP ASE", "dsp"),
FeatureInfo(@This()).createWithSubfeatures(.Dspr2, "dspr2", "Mips DSP-R2 ASE", "dspr2", &[_]@This() {
.Dsp,
}),
FeatureInfo(@This()).createWithSubfeatures(.Dspr3, "dspr3", "Mips DSP-R3 ASE", "dspr3", &[_]@This() {
.Dsp,
}),
FeatureInfo(@This()).create(.Eva, "eva", "Mips EVA ASE", "eva"),
FeatureInfo(@This()).create(.Fp64, "fp64", "Support 64-bit FP registers", "fp64"),
FeatureInfo(@This()).create(.Fpxx, "fpxx", "Support for FPXX", "fpxx"),
FeatureInfo(@This()).create(.Ginv, "ginv", "Mips Global Invalidate ASE", "ginv"),
FeatureInfo(@This()).create(.Gp64, "gp64", "General Purpose Registers are 64-bit wide", "gp64"),
FeatureInfo(@This()).create(.LongCalls, "long-calls", "Disable use of the jal instruction", "long-calls"),
FeatureInfo(@This()).create(.Msa, "msa", "Mips MSA ASE", "msa"),
FeatureInfo(@This()).create(.Mt, "mt", "Mips MT ASE", "mt"),
FeatureInfo(@This()).create(.Nomadd4, "nomadd4", "Disable 4-operand madd.fmt and related instructions", "nomadd4"),
FeatureInfo(@This()).create(.Micromips, "micromips", "microMips mode", "micromips"),
FeatureInfo(@This()).create(.Mips1, "mips1", "Mips I ISA Support [highly experimental]", "mips1"),
FeatureInfo(@This()).createWithSubfeatures(.Mips2, "mips2", "Mips II ISA Support [highly experimental]", "mips2", &[_]@This() {
.Mips1,
}),
FeatureInfo(@This()).createWithSubfeatures(.Mips3, "mips3", "MIPS III ISA Support [highly experimental]", "mips3", &[_]@This() {
.Mips3_32r2,
.Fp64,
.Gp64,
.Mips1,
.Mips3_32,
}),
FeatureInfo(@This()).create(.Mips3_32, "mips3_32", "Subset of MIPS-III that is also in MIPS32 [highly experimental]", "mips3_32"),
FeatureInfo(@This()).create(.Mips3_32r2, "mips3_32r2", "Subset of MIPS-III that is also in MIPS32r2 [highly experimental]", "mips3_32r2"),
FeatureInfo(@This()).createWithSubfeatures(.Mips4, "mips4", "MIPS IV ISA Support", "mips4", &[_]@This() {
.Mips3_32r2,
.Mips4_32r2,
.Fp64,
.Gp64,
.Mips4_32,
.Mips1,
.Mips3_32,
}),
FeatureInfo(@This()).create(.Mips4_32, "mips4_32", "Subset of MIPS-IV that is also in MIPS32 [highly experimental]", "mips4_32"),
FeatureInfo(@This()).create(.Mips4_32r2, "mips4_32r2", "Subset of MIPS-IV that is also in MIPS32r2 [highly experimental]", "mips4_32r2"),
FeatureInfo(@This()).createWithSubfeatures(.Mips5, "mips5", "MIPS V ISA Support [highly experimental]", "mips5", &[_]@This() {
.Mips5_32r2,
.Mips4_32r2,
.Mips3_32r2,
.Gp64,
.Fp64,
.Mips4_32,
.Mips1,
.Mips3_32,
}),
FeatureInfo(@This()).create(.Mips5_32r2, "mips5_32r2", "Subset of MIPS-V that is also in MIPS32r2 [highly experimental]", "mips5_32r2"),
FeatureInfo(@This()).create(.Mips16, "mips16", "Mips16 mode", "mips16"),
FeatureInfo(@This()).createWithSubfeatures(.Mips32, "mips32", "Mips32 ISA Support", "mips32", &[_]@This() {
.Mips4_32,
.Mips1,
.Mips3_32,
}),
FeatureInfo(@This()).createWithSubfeatures(.Mips32r2, "mips32r2", "Mips32r2 ISA Support", "mips32r2", &[_]@This() {
.Mips5_32r2,
.Mips4_32r2,
.Mips3_32r2,
.Mips4_32,
.Mips1,
.Mips3_32,
}),
FeatureInfo(@This()).createWithSubfeatures(.Mips32r3, "mips32r3", "Mips32r3 ISA Support", "mips32r3", &[_]@This() {
.Mips5_32r2,
.Mips3_32r2,
.Mips4_32r2,
.Mips4_32,
.Mips1,
.Mips3_32,
}),
FeatureInfo(@This()).createWithSubfeatures(.Mips32r5, "mips32r5", "Mips32r5 ISA Support", "mips32r5", &[_]@This() {
.Mips5_32r2,
.Mips3_32r2,
.Mips4_32r2,
.Mips4_32,
.Mips1,
.Mips3_32,
}),
FeatureInfo(@This()).createWithSubfeatures(.Mips32r6, "mips32r6", "Mips32r6 ISA Support [experimental]", "mips32r6", &[_]@This() {
.Mips5_32r2,
.Mips3_32r2,
.Mips4_32r2,
.Abs2008,
.Nan2008,
.Fp64,
.Mips4_32,
.Mips1,
.Mips3_32,
}),
FeatureInfo(@This()).createWithSubfeatures(.Mips64, "mips64", "Mips64 ISA Support", "mips64", &[_]@This() {
.Mips5_32r2,
.Mips3_32r2,
.Mips4_32r2,
.Gp64,
.Fp64,
.Mips4_32,
.Mips1,
.Mips3_32,
}),
FeatureInfo(@This()).createWithSubfeatures(.Mips64r2, "mips64r2", "Mips64r2 ISA Support", "mips64r2", &[_]@This() {
.Mips5_32r2,
.Mips3_32r2,
.Mips4_32r2,
.Gp64,
.Fp64,
.Mips4_32,
.Mips1,
.Mips3_32,
}),
FeatureInfo(@This()).createWithSubfeatures(.Mips64r3, "mips64r3", "Mips64r3 ISA Support", "mips64r3", &[_]@This() {
.Mips5_32r2,
.Mips3_32r2,
.Mips4_32r2,
.Gp64,
.Fp64,
.Mips4_32,
.Mips1,
.Mips3_32,
}),
FeatureInfo(@This()).createWithSubfeatures(.Mips64r5, "mips64r5", "Mips64r5 ISA Support", "mips64r5", &[_]@This() {
.Mips5_32r2,
.Mips3_32r2,
.Mips4_32r2,
.Gp64,
.Fp64,
.Mips4_32,
.Mips1,
.Mips3_32,
}),
FeatureInfo(@This()).createWithSubfeatures(.Mips64r6, "mips64r6", "Mips64r6 ISA Support [experimental]", "mips64r6", &[_]@This() {
.Mips5_32r2,
.Mips3_32r2,
.Nan2008,
.Abs2008,
.Mips4_32r2,
.Fp64,
.Gp64,
.Mips4_32,
.Mips1,
.Mips3_32,
}),
FeatureInfo(@This()).create(.Nan2008, "nan2008", "IEEE 754-2008 NaN encoding", "nan2008"),
FeatureInfo(@This()).create(.Noabicalls, "noabicalls", "Disable SVR4-style position-independent code", "noabicalls"),
FeatureInfo(@This()).create(.Nooddspreg, "nooddspreg", "Disable odd numbered single-precision registers", "nooddspreg"),
FeatureInfo(@This()).create(.Ptr64, "ptr64", "Pointers are 64-bit wide", "ptr64"),
FeatureInfo(@This()).create(.SingleFloat, "single-float", "Only supports single precision float", "single-float"),
FeatureInfo(@This()).create(.SoftFloat, "soft-float", "Does not support floating point instructions", "soft-float"),
FeatureInfo(@This()).create(.Sym32, "sym32", "Symbols are 32 bit on Mips64", "sym32"),
FeatureInfo(@This()).create(.UseIndirectJumpHazard, "use-indirect-jump-hazard", "Use indirect jump guards to prevent certain speculation based attacks", "use-indirect-jump-hazard"),
FeatureInfo(@This()).create(.UseTccInDiv, "use-tcc-in-div", "Force the assembler to use trapping", "use-tcc-in-div"),
FeatureInfo(@This()).create(.Vfpu, "vfpu", "Enable vector FPU instructions", "vfpu"),
FeatureInfo(@This()).create(.Virt, "virt", "Mips Virtualization ASE", "virt"),
FeatureInfo(@This()).create(.Xgot, "xgot", "Assume 32-bit GOT", "xgot"),
FeatureInfo(@This()).createWithSubfeatures(.P5600, "p5600", "The P5600 Processor", "p5600", &[_]@This() {
.Mips5_32r2,
.Mips3_32r2,
.Mips4_32r2,
.Mips4_32,
.Mips1,
.Mips3_32,
}),
};
};

19
lib/std/target/feature/Msp430Feature.zig
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@@ -1,19 +0,0 @@
const FeatureInfo = @import("std").target.feature.FeatureInfo;
pub const Msp430Feature = enum {
Hwmult16,
Hwmult32,
Hwmultf5,
Ext,
pub fn getInfo(self: @This()) FeatureInfo(@This()) {
return feature_infos[@enumToInt(self)];
}
pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
FeatureInfo(@This()).create(.Hwmult16, "hwmult16", "Enable 16-bit hardware multiplier", "hwmult16"),
FeatureInfo(@This()).create(.Hwmult32, "hwmult32", "Enable 32-bit hardware multiplier", "hwmult32"),
FeatureInfo(@This()).create(.Hwmultf5, "hwmultf5", "Enable F5 series hardware multiplier", "hwmultf5"),
FeatureInfo(@This()).create(.Ext, "ext", "Enable MSP430-X extensions", "ext"),
};
};

61
lib/std/target/feature/NvptxFeature.zig
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const FeatureInfo = @import("std").target.feature.FeatureInfo;
pub const NvptxFeature = enum {
Ptx32,
Ptx40,
Ptx41,
Ptx42,
Ptx43,
Ptx50,
Ptx60,
Ptx61,
Ptx63,
Ptx64,
Sm_20,
Sm_21,
Sm_30,
Sm_32,
Sm_35,
Sm_37,
Sm_50,
Sm_52,
Sm_53,
Sm_60,
Sm_61,
Sm_62,
Sm_70,
Sm_72,
Sm_75,
pub fn getInfo(self: @This()) FeatureInfo(@This()) {
return feature_infos[@enumToInt(self)];
}
pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
FeatureInfo(@This()).create(.Ptx32, "ptx32", "Use PTX version 3.2", "ptx32"),
FeatureInfo(@This()).create(.Ptx40, "ptx40", "Use PTX version 4.0", "ptx40"),
FeatureInfo(@This()).create(.Ptx41, "ptx41", "Use PTX version 4.1", "ptx41"),
FeatureInfo(@This()).create(.Ptx42, "ptx42", "Use PTX version 4.2", "ptx42"),
FeatureInfo(@This()).create(.Ptx43, "ptx43", "Use PTX version 4.3", "ptx43"),
FeatureInfo(@This()).create(.Ptx50, "ptx50", "Use PTX version 5.0", "ptx50"),
FeatureInfo(@This()).create(.Ptx60, "ptx60", "Use PTX version 6.0", "ptx60"),
FeatureInfo(@This()).create(.Ptx61, "ptx61", "Use PTX version 6.1", "ptx61"),
FeatureInfo(@This()).create(.Ptx63, "ptx63", "Use PTX version 6.3", "ptx63"),
FeatureInfo(@This()).create(.Ptx64, "ptx64", "Use PTX version 6.4", "ptx64"),
FeatureInfo(@This()).create(.Sm_20, "sm_20", "Target SM 2.0", "sm_20"),
FeatureInfo(@This()).create(.Sm_21, "sm_21", "Target SM 2.1", "sm_21"),
FeatureInfo(@This()).create(.Sm_30, "sm_30", "Target SM 3.0", "sm_30"),
FeatureInfo(@This()).create(.Sm_32, "sm_32", "Target SM 3.2", "sm_32"),
FeatureInfo(@This()).create(.Sm_35, "sm_35", "Target SM 3.5", "sm_35"),
FeatureInfo(@This()).create(.Sm_37, "sm_37", "Target SM 3.7", "sm_37"),
FeatureInfo(@This()).create(.Sm_50, "sm_50", "Target SM 5.0", "sm_50"),
FeatureInfo(@This()).create(.Sm_52, "sm_52", "Target SM 5.2", "sm_52"),
FeatureInfo(@This()).create(.Sm_53, "sm_53", "Target SM 5.3", "sm_53"),
FeatureInfo(@This()).create(.Sm_60, "sm_60", "Target SM 6.0", "sm_60"),
FeatureInfo(@This()).create(.Sm_61, "sm_61", "Target SM 6.1", "sm_61"),
FeatureInfo(@This()).create(.Sm_62, "sm_62", "Target SM 6.2", "sm_62"),
FeatureInfo(@This()).create(.Sm_70, "sm_70", "Target SM 7.0", "sm_70"),
FeatureInfo(@This()).create(.Sm_72, "sm_72", "Target SM 7.2", "sm_72"),
FeatureInfo(@This()).create(.Sm_75, "sm_75", "Target SM 7.5", "sm_75"),
};
};

163
lib/std/target/feature/PowerPcFeature.zig
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const FeatureInfo = @import("std").target.feature.FeatureInfo;
pub const PowerPcFeature = enum {
Bit64,
Bitregs64,
Altivec,
Bpermd,
Booke,
Cmpb,
Crbits,
DirectMove,
E500,
Extdiv,
Fcpsgn,
Fpcvt,
Fprnd,
Fpu,
Fre,
Fres,
Frsqrte,
Frsqrtes,
Fsqrt,
Float128,
Htm,
HardFloat,
Icbt,
IsaV30Instructions,
Isel,
InvariantFunctionDescriptors,
Ldbrx,
Lfiwax,
Longcall,
Mfocrf,
Msync,
Power8Altivec,
Crypto,
Power8Vector,
Power9Altivec,
Power9Vector,
Popcntd,
Ppc4xx,
Ppc6xx,
PpcPostraSched,
PpcPreraSched,
PartwordAtomics,
Qpx,
Recipprec,
Spe,
Stfiwx,
SecurePlt,
SlowPopcntd,
TwoConstNr,
Vsx,
VectorsUseTwoUnits,
pub fn getInfo(self: @This()) FeatureInfo(@This()) {
return feature_infos[@enumToInt(self)];
}
pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
FeatureInfo(@This()).create(.Bit64, "64bit", "Enable 64-bit instructions", "64bit"),
FeatureInfo(@This()).create(.Bitregs64, "64bitregs", "Enable 64-bit registers usage for ppc32 [beta]", "64bitregs"),
FeatureInfo(@This()).createWithSubfeatures(.Altivec, "altivec", "Enable Altivec instructions", "altivec", &[_]@This() {
.HardFloat,
}),
FeatureInfo(@This()).create(.Bpermd, "bpermd", "Enable the bpermd instruction", "bpermd"),
FeatureInfo(@This()).createWithSubfeatures(.Booke, "booke", "Enable Book E instructions", "booke", &[_]@This() {
.Icbt,
}),
FeatureInfo(@This()).create(.Cmpb, "cmpb", "Enable the cmpb instruction", "cmpb"),
FeatureInfo(@This()).create(.Crbits, "crbits", "Use condition-register bits individually", "crbits"),
FeatureInfo(@This()).createWithSubfeatures(.DirectMove, "direct-move", "Enable Power8 direct move instructions", "direct-move", &[_]@This() {
.HardFloat,
}),
FeatureInfo(@This()).create(.E500, "e500", "Enable E500/E500mc instructions", "e500"),
FeatureInfo(@This()).create(.Extdiv, "extdiv", "Enable extended divide instructions", "extdiv"),
FeatureInfo(@This()).createWithSubfeatures(.Fcpsgn, "fcpsgn", "Enable the fcpsgn instruction", "fcpsgn", &[_]@This() {
.HardFloat,
}),
FeatureInfo(@This()).createWithSubfeatures(.Fpcvt, "fpcvt", "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions", "fpcvt", &[_]@This() {
.HardFloat,
}),
FeatureInfo(@This()).createWithSubfeatures(.Fprnd, "fprnd", "Enable the fri[mnpz] instructions", "fprnd", &[_]@This() {
.HardFloat,
}),
FeatureInfo(@This()).createWithSubfeatures(.Fpu, "fpu", "Enable classic FPU instructions", "fpu", &[_]@This() {
.HardFloat,
}),
FeatureInfo(@This()).createWithSubfeatures(.Fre, "fre", "Enable the fre instruction", "fre", &[_]@This() {
.HardFloat,
}),
FeatureInfo(@This()).createWithSubfeatures(.Fres, "fres", "Enable the fres instruction", "fres", &[_]@This() {
.HardFloat,
}),
FeatureInfo(@This()).createWithSubfeatures(.Frsqrte, "frsqrte", "Enable the frsqrte instruction", "frsqrte", &[_]@This() {
.HardFloat,
}),
FeatureInfo(@This()).createWithSubfeatures(.Frsqrtes, "frsqrtes", "Enable the frsqrtes instruction", "frsqrtes", &[_]@This() {
.HardFloat,
}),
FeatureInfo(@This()).createWithSubfeatures(.Fsqrt, "fsqrt", "Enable the fsqrt instruction", "fsqrt", &[_]@This() {
.HardFloat,
}),
FeatureInfo(@This()).createWithSubfeatures(.Float128, "float128", "Enable the __float128 data type for IEEE-754R Binary128.", "float128", &[_]@This() {
.HardFloat,
}),
FeatureInfo(@This()).create(.Htm, "htm", "Enable Hardware Transactional Memory instructions", "htm"),
FeatureInfo(@This()).create(.HardFloat, "hard-float", "Enable floating-point instructions", "hard-float"),
FeatureInfo(@This()).create(.Icbt, "icbt", "Enable icbt instruction", "icbt"),
FeatureInfo(@This()).create(.IsaV30Instructions, "isa-v30-instructions", "Enable instructions added in ISA 3.0.", "isa-v30-instructions"),
FeatureInfo(@This()).create(.Isel, "isel", "Enable the isel instruction", "isel"),
FeatureInfo(@This()).create(.InvariantFunctionDescriptors, "invariant-function-descriptors", "Assume function descriptors are invariant", "invariant-function-descriptors"),
FeatureInfo(@This()).create(.Ldbrx, "ldbrx", "Enable the ldbrx instruction", "ldbrx"),
FeatureInfo(@This()).createWithSubfeatures(.Lfiwax, "lfiwax", "Enable the lfiwax instruction", "lfiwax", &[_]@This() {
.HardFloat,
}),
FeatureInfo(@This()).create(.Longcall, "longcall", "Always use indirect calls", "longcall"),
FeatureInfo(@This()).create(.Mfocrf, "mfocrf", "Enable the MFOCRF instruction", "mfocrf"),
FeatureInfo(@This()).createWithSubfeatures(.Msync, "msync", "Has only the msync instruction instead of sync", "msync", &[_]@This() {
.Icbt,
}),
FeatureInfo(@This()).createWithSubfeatures(.Power8Altivec, "power8-altivec", "Enable POWER8 Altivec instructions", "power8-altivec", &[_]@This() {
.HardFloat,
}),
FeatureInfo(@This()).createWithSubfeatures(.Crypto, "crypto", "Enable POWER8 Crypto instructions", "crypto", &[_]@This() {
.HardFloat,
}),
FeatureInfo(@This()).createWithSubfeatures(.Power8Vector, "power8-vector", "Enable POWER8 vector instructions", "power8-vector", &[_]@This() {
.HardFloat,
}),
FeatureInfo(@This()).createWithSubfeatures(.Power9Altivec, "power9-altivec", "Enable POWER9 Altivec instructions", "power9-altivec", &[_]@This() {
.IsaV30Instructions,
.HardFloat,
}),
FeatureInfo(@This()).createWithSubfeatures(.Power9Vector, "power9-vector", "Enable POWER9 vector instructions", "power9-vector", &[_]@This() {
.IsaV30Instructions,
.HardFloat,
}),
FeatureInfo(@This()).create(.Popcntd, "popcntd", "Enable the popcnt[dw] instructions", "popcntd"),
FeatureInfo(@This()).create(.Ppc4xx, "ppc4xx", "Enable PPC 4xx instructions", "ppc4xx"),
FeatureInfo(@This()).create(.Ppc6xx, "ppc6xx", "Enable PPC 6xx instructions", "ppc6xx"),
FeatureInfo(@This()).create(.PpcPostraSched, "ppc-postra-sched", "Use PowerPC post-RA scheduling strategy", "ppc-postra-sched"),
FeatureInfo(@This()).create(.PpcPreraSched, "ppc-prera-sched", "Use PowerPC pre-RA scheduling strategy", "ppc-prera-sched"),
FeatureInfo(@This()).create(.PartwordAtomics, "partword-atomics", "Enable l[bh]arx and st[bh]cx.", "partword-atomics"),
FeatureInfo(@This()).createWithSubfeatures(.Qpx, "qpx", "Enable QPX instructions", "qpx", &[_]@This() {
.HardFloat,
}),
FeatureInfo(@This()).create(.Recipprec, "recipprec", "Assume higher precision reciprocal estimates", "recipprec"),
FeatureInfo(@This()).createWithSubfeatures(.Spe, "spe", "Enable SPE instructions", "spe", &[_]@This() {
.HardFloat,
}),
FeatureInfo(@This()).createWithSubfeatures(.Stfiwx, "stfiwx", "Enable the stfiwx instruction", "stfiwx", &[_]@This() {
.HardFloat,
}),
FeatureInfo(@This()).create(.SecurePlt, "secure-plt", "Enable secure plt mode", "secure-plt"),
FeatureInfo(@This()).create(.SlowPopcntd, "slow-popcntd", "Has slow popcnt[dw] instructions", "slow-popcntd"),
FeatureInfo(@This()).create(.TwoConstNr, "two-const-nr", "Requires two constant Newton-Raphson computation", "two-const-nr"),
FeatureInfo(@This()).createWithSubfeatures(.Vsx, "vsx", "Enable VSX instructions", "vsx", &[_]@This() {
.HardFloat,
}),
FeatureInfo(@This()).create(.VectorsUseTwoUnits, "vectors-use-two-units", "Vectors use two units", "vectors-use-two-units"),
};
};

31
lib/std/target/feature/RiscVFeature.zig
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const FeatureInfo = @import("std").target.feature.FeatureInfo;
pub const RiscVFeature = enum {
Bit64,
E,
RvcHints,
Relax,
A,
C,
D,
F,
M,
pub fn getInfo(self: @This()) FeatureInfo(@This()) {
return feature_infos[@enumToInt(self)];
}
pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
FeatureInfo(@This()).create(.Bit64, "64bit", "Implements RV64", "64bit"),
FeatureInfo(@This()).create(.E, "e", "Implements RV32E (provides 16 rather than 32 GPRs)", "e"),
FeatureInfo(@This()).create(.RvcHints, "rvc-hints", "Enable RVC Hint Instructions.", "rvc-hints"),
FeatureInfo(@This()).create(.Relax, "relax", "Enable Linker relaxation.", "relax"),
FeatureInfo(@This()).create(.A, "a", "'A' (Atomic Instructions)", "a"),
FeatureInfo(@This()).create(.C, "c", "'C' (Compressed Instructions)", "c"),
FeatureInfo(@This()).createWithSubfeatures(.D, "d", "'D' (Double-Precision Floating-Point)", "d", &[_]@This() {
.F,
}),
FeatureInfo(@This()).create(.F, "f", "'F' (Single-Precision Floating-Point)", "f"),
FeatureInfo(@This()).create(.M, "m", "'M' (Integer Multiplication and Division)", "m"),
};
};

49
lib/std/target/feature/SparcFeature.zig
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@@ -1,49 +0,0 @@
const FeatureInfo = @import("std").target.feature.FeatureInfo;
pub const SparcFeature = enum {
Detectroundchange,
HardQuadFloat,
Leon,
NoFmuls,
NoFsmuld,
Leonpwrpsr,
SoftFloat,
SoftMulDiv,
DeprecatedV8,
V9,
Vis,
Vis2,
Vis3,
Fixallfdivsqrt,
Insertnopload,
Hasleoncasa,
Leoncyclecounter,
Hasumacsmac,
Popc,
pub fn getInfo(self: @This()) FeatureInfo(@This()) {
return feature_infos[@enumToInt(self)];
}
pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
FeatureInfo(@This()).create(.Detectroundchange, "detectroundchange", "LEON3 erratum detection: Detects any rounding mode change request: use only the round-to-nearest rounding mode", "detectroundchange"),
FeatureInfo(@This()).create(.HardQuadFloat, "hard-quad-float", "Enable quad-word floating point instructions", "hard-quad-float"),
FeatureInfo(@This()).create(.Leon, "leon", "Enable LEON extensions", "leon"),
FeatureInfo(@This()).create(.NoFmuls, "no-fmuls", "Disable the fmuls instruction.", "no-fmuls"),
FeatureInfo(@This()).create(.NoFsmuld, "no-fsmuld", "Disable the fsmuld instruction.", "no-fsmuld"),
FeatureInfo(@This()).create(.Leonpwrpsr, "leonpwrpsr", "Enable the PWRPSR instruction", "leonpwrpsr"),
FeatureInfo(@This()).create(.SoftFloat, "soft-float", "Use software emulation for floating point", "soft-float"),
FeatureInfo(@This()).create(.SoftMulDiv, "soft-mul-div", "Use software emulation for integer multiply and divide", "soft-mul-div"),
FeatureInfo(@This()).create(.DeprecatedV8, "deprecated-v8", "Enable deprecated V8 instructions in V9 mode", "deprecated-v8"),
FeatureInfo(@This()).create(.V9, "v9", "Enable SPARC-V9 instructions", "v9"),
FeatureInfo(@This()).create(.Vis, "vis", "Enable UltraSPARC Visual Instruction Set extensions", "vis"),
FeatureInfo(@This()).create(.Vis2, "vis2", "Enable Visual Instruction Set extensions II", "vis2"),
FeatureInfo(@This()).create(.Vis3, "vis3", "Enable Visual Instruction Set extensions III", "vis3"),
FeatureInfo(@This()).create(.Fixallfdivsqrt, "fixallfdivsqrt", "LEON erratum fix: Fix FDIVS/FDIVD/FSQRTS/FSQRTD instructions with NOPs and floating-point store", "fixallfdivsqrt"),
FeatureInfo(@This()).create(.Insertnopload, "insertnopload", "LEON3 erratum fix: Insert a NOP instruction after every single-cycle load instruction when the next instruction is another load/store instruction", "insertnopload"),
FeatureInfo(@This()).create(.Hasleoncasa, "hasleoncasa", "Enable CASA instruction for LEON3 and LEON4 processors", "hasleoncasa"),
FeatureInfo(@This()).create(.Leoncyclecounter, "leoncyclecounter", "Use the Leon cycle counter register", "leoncyclecounter"),
FeatureInfo(@This()).create(.Hasumacsmac, "hasumacsmac", "Enable UMAC and SMAC for LEON3 and LEON4 processors", "hasumacsmac"),
FeatureInfo(@This()).create(.Popc, "popc", "Use the popc (population count) instruction", "popc"),
};
};

81
lib/std/target/feature/SystemZFeature.zig
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@@ -1,81 +0,0 @@
const FeatureInfo = @import("std").target.feature.FeatureInfo;
pub const SystemZFeature = enum {
DfpPackedConversion,
DfpZonedConversion,
DeflateConversion,
DistinctOps,
EnhancedDat2,
EnhancedSort,
ExecutionHint,
FpExtension,
FastSerialization,
GuardedStorage,
HighWord,
InsertReferenceBitsMultiple,
InterlockedAccess1,
LoadAndTrap,
LoadAndZeroRightmostByte,
LoadStoreOnCond,
LoadStoreOnCond2,
MessageSecurityAssistExtension3,
MessageSecurityAssistExtension4,
MessageSecurityAssistExtension5,
MessageSecurityAssistExtension7,
MessageSecurityAssistExtension8,
MessageSecurityAssistExtension9,
MiscellaneousExtensions,
MiscellaneousExtensions2,
MiscellaneousExtensions3,
PopulationCount,
ProcessorAssist,
ResetReferenceBitsMultiple,
TransactionalExecution,
Vector,
VectorEnhancements1,
VectorEnhancements2,
VectorPackedDecimal,
VectorPackedDecimalEnhancement,
pub fn getInfo(self: @This()) FeatureInfo(@This()) {
return feature_infos[@enumToInt(self)];
}
pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
FeatureInfo(@This()).create(.DfpPackedConversion, "dfp-packed-conversion", "Assume that the DFP packed-conversion facility is installed", "dfp-packed-conversion"),
FeatureInfo(@This()).create(.DfpZonedConversion, "dfp-zoned-conversion", "Assume that the DFP zoned-conversion facility is installed", "dfp-zoned-conversion"),
FeatureInfo(@This()).create(.DeflateConversion, "deflate-conversion", "Assume that the deflate-conversion facility is installed", "deflate-conversion"),
FeatureInfo(@This()).create(.DistinctOps, "distinct-ops", "Assume that the distinct-operands facility is installed", "distinct-ops"),
FeatureInfo(@This()).create(.EnhancedDat2, "enhanced-dat-2", "Assume that the enhanced-DAT facility 2 is installed", "enhanced-dat-2"),
FeatureInfo(@This()).create(.EnhancedSort, "enhanced-sort", "Assume that the enhanced-sort facility is installed", "enhanced-sort"),
FeatureInfo(@This()).create(.ExecutionHint, "execution-hint", "Assume that the execution-hint facility is installed", "execution-hint"),
FeatureInfo(@This()).create(.FpExtension, "fp-extension", "Assume that the floating-point extension facility is installed", "fp-extension"),
FeatureInfo(@This()).create(.FastSerialization, "fast-serialization", "Assume that the fast-serialization facility is installed", "fast-serialization"),
FeatureInfo(@This()).create(.GuardedStorage, "guarded-storage", "Assume that the guarded-storage facility is installed", "guarded-storage"),
FeatureInfo(@This()).create(.HighWord, "high-word", "Assume that the high-word facility is installed", "high-word"),
FeatureInfo(@This()).create(.InsertReferenceBitsMultiple, "insert-reference-bits-multiple", "Assume that the insert-reference-bits-multiple facility is installed", "insert-reference-bits-multiple"),
FeatureInfo(@This()).create(.InterlockedAccess1, "interlocked-access1", "Assume that interlocked-access facility 1 is installed", "interlocked-access1"),
FeatureInfo(@This()).create(.LoadAndTrap, "load-and-trap", "Assume that the load-and-trap facility is installed", "load-and-trap"),
FeatureInfo(@This()).create(.LoadAndZeroRightmostByte, "load-and-zero-rightmost-byte", "Assume that the load-and-zero-rightmost-byte facility is installed", "load-and-zero-rightmost-byte"),
FeatureInfo(@This()).create(.LoadStoreOnCond, "load-store-on-cond", "Assume that the load/store-on-condition facility is installed", "load-store-on-cond"),
FeatureInfo(@This()).create(.LoadStoreOnCond2, "load-store-on-cond-2", "Assume that the load/store-on-condition facility 2 is installed", "load-store-on-cond-2"),
FeatureInfo(@This()).create(.MessageSecurityAssistExtension3, "message-security-assist-extension3", "Assume that the message-security-assist extension facility 3 is installed", "message-security-assist-extension3"),
FeatureInfo(@This()).create(.MessageSecurityAssistExtension4, "message-security-assist-extension4", "Assume that the message-security-assist extension facility 4 is installed", "message-security-assist-extension4"),
FeatureInfo(@This()).create(.MessageSecurityAssistExtension5, "message-security-assist-extension5", "Assume that the message-security-assist extension facility 5 is installed", "message-security-assist-extension5"),
FeatureInfo(@This()).create(.MessageSecurityAssistExtension7, "message-security-assist-extension7", "Assume that the message-security-assist extension facility 7 is installed", "message-security-assist-extension7"),
FeatureInfo(@This()).create(.MessageSecurityAssistExtension8, "message-security-assist-extension8", "Assume that the message-security-assist extension facility 8 is installed", "message-security-assist-extension8"),
FeatureInfo(@This()).create(.MessageSecurityAssistExtension9, "message-security-assist-extension9", "Assume that the message-security-assist extension facility 9 is installed", "message-security-assist-extension9"),
FeatureInfo(@This()).create(.MiscellaneousExtensions, "miscellaneous-extensions", "Assume that the miscellaneous-extensions facility is installed", "miscellaneous-extensions"),
FeatureInfo(@This()).create(.MiscellaneousExtensions2, "miscellaneous-extensions-2", "Assume that the miscellaneous-extensions facility 2 is installed", "miscellaneous-extensions-2"),
FeatureInfo(@This()).create(.MiscellaneousExtensions3, "miscellaneous-extensions-3", "Assume that the miscellaneous-extensions facility 3 is installed", "miscellaneous-extensions-3"),
FeatureInfo(@This()).create(.PopulationCount, "population-count", "Assume that the population-count facility is installed", "population-count"),
FeatureInfo(@This()).create(.ProcessorAssist, "processor-assist", "Assume that the processor-assist facility is installed", "processor-assist"),
FeatureInfo(@This()).create(.ResetReferenceBitsMultiple, "reset-reference-bits-multiple", "Assume that the reset-reference-bits-multiple facility is installed", "reset-reference-bits-multiple"),
FeatureInfo(@This()).create(.TransactionalExecution, "transactional-execution", "Assume that the transactional-execution facility is installed", "transactional-execution"),
FeatureInfo(@This()).create(.Vector, "vector", "Assume that the vectory facility is installed", "vector"),
FeatureInfo(@This()).create(.VectorEnhancements1, "vector-enhancements-1", "Assume that the vector enhancements facility 1 is installed", "vector-enhancements-1"),
FeatureInfo(@This()).create(.VectorEnhancements2, "vector-enhancements-2", "Assume that the vector enhancements facility 2 is installed", "vector-enhancements-2"),
FeatureInfo(@This()).create(.VectorPackedDecimal, "vector-packed-decimal", "Assume that the vector packed decimal facility is installed", "vector-packed-decimal"),
FeatureInfo(@This()).create(.VectorPackedDecimalEnhancement, "vector-packed-decimal-enhancement", "Assume that the vector packed decimal enhancement facility is installed", "vector-packed-decimal-enhancement"),
};
};

33
lib/std/target/feature/WebAssemblyFeature.zig
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@@ -1,33 +0,0 @@
const FeatureInfo = @import("std").target.feature.FeatureInfo;
pub const WebAssemblyFeature = enum {
Atomics,
BulkMemory,
ExceptionHandling,
Multivalue,
MutableGlobals,
NontrappingFptoint,
Simd128,
SignExt,
TailCall,
UnimplementedSimd128,
pub fn getInfo(self: @This()) FeatureInfo(@This()) {
return feature_infos[@enumToInt(self)];
}
pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
FeatureInfo(@This()).create(.Atomics, "atomics", "Enable Atomics", "atomics"),
FeatureInfo(@This()).create(.BulkMemory, "bulk-memory", "Enable bulk memory operations", "bulk-memory"),
FeatureInfo(@This()).create(.ExceptionHandling, "exception-handling", "Enable Wasm exception handling", "exception-handling"),
FeatureInfo(@This()).create(.Multivalue, "multivalue", "Enable multivalue blocks, instructions, and functions", "multivalue"),
FeatureInfo(@This()).create(.MutableGlobals, "mutable-globals", "Enable mutable globals", "mutable-globals"),
FeatureInfo(@This()).create(.NontrappingFptoint, "nontrapping-fptoint", "Enable non-trapping float-to-int conversion operators", "nontrapping-fptoint"),
FeatureInfo(@This()).create(.Simd128, "simd128", "Enable 128-bit SIMD", "simd128"),
FeatureInfo(@This()).create(.SignExt, "sign-ext", "Enable sign extension operators", "sign-ext"),
FeatureInfo(@This()).create(.TailCall, "tail-call", "Enable tail call instructions", "tail-call"),
FeatureInfo(@This()).createWithSubfeatures(.UnimplementedSimd128, "unimplemented-simd128", "Enable 128-bit SIMD not yet implemented in engines", "unimplemented-simd128", &[_]@This() {
.Simd128,
}),
};
};

342
lib/std/target/feature/X86Feature.zig
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@@ -1,342 +0,0 @@
const FeatureInfo = @import("std").target.feature.FeatureInfo;
pub const X86Feature = enum {
Dnow3,
Dnowa3,
Bit64,
Adx,
Aes,
Avx,
Avx2,
Avx512f,
Avx512bf16,
Avx512bitalg,
Bmi,
Bmi2,
Avx512bw,
Branchfusion,
Avx512cd,
Cldemote,
Clflushopt,
Clwb,
Clzero,
Cmov,
Cx8,
Cx16,
Avx512dq,
Mpx,
Enqcmd,
Avx512er,
Ermsb,
F16c,
Fma,
Fma4,
Fsgsbase,
Fxsr,
Fast11bytenop,
Fast15bytenop,
FastBextr,
FastHops,
FastLzcnt,
FastPartialYmmOrZmmWrite,
FastShldRotate,
FastScalarFsqrt,
FastScalarShiftMasks,
FastVariableShuffle,
FastVectorFsqrt,
FastVectorShiftMasks,
Gfni,
FastGather,
Avx512ifma,
Invpcid,
Sahf,
LeaSp,
LeaUsesAg,
Lwp,
Lzcnt,
FalseDepsLzcntTzcnt,
Mmx,
Movbe,
Movdir64b,
Movdiri,
Mwaitx,
Macrofusion,
MergeToThreewayBranch,
Nopl,
Pclmul,
Pconfig,
Avx512pf,
Pku,
Popcnt,
FalseDepsPopcnt,
Prefetchwt1,
Prfchw,
Ptwrite,
PadShortFunctions,
Prefer128Bit,
Prefer256Bit,
Rdpid,
Rdrnd,
Rdseed,
Rtm,
Retpoline,
RetpolineExternalThunk,
RetpolineIndirectBranches,
RetpolineIndirectCalls,
Sgx,
Sha,
Shstk,
Sse,
Sse2,
Sse3,
Sse4a,
Sse41,
Sse42,
SseUnalignedMem,
Ssse3,
Slow3opsLea,
IdivlToDivb,
IdivqToDivl,
SlowIncdec,
SlowLea,
SlowPmaddwd,
SlowPmulld,
SlowShld,
SlowTwoMemOps,
SlowUnalignedMem16,
SlowUnalignedMem32,
SoftFloat,
Tbm,
UseAa,
Vaes,
Avx512vbmi,
Avx512vbmi2,
Avx512vl,
Avx512vnni,
Avx512vp2intersect,
Vpclmulqdq,
Avx512vpopcntdq,
Waitpkg,
Wbnoinvd,
X87,
Xop,
Xsave,
Xsavec,
Xsaveopt,
Xsaves,
BitMode16,
BitMode32,
BitMode64,
pub fn getInfo(self: @This()) FeatureInfo(@This()) {
return feature_infos[@enumToInt(self)];
}
pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
FeatureInfo(@This()).createWithSubfeatures(.Dnow3, "3dnow", "Enable 3DNow! instructions", "3dnow", &[_]@This() {
.Mmx,
}),
FeatureInfo(@This()).createWithSubfeatures(.Dnowa3, "3dnowa", "Enable 3DNow! Athlon instructions", "3dnowa", &[_]@This() {
.Mmx,
}),
FeatureInfo(@This()).create(.Bit64, "64bit", "Support 64-bit instructions", "64bit"),
FeatureInfo(@This()).create(.Adx, "adx", "Support ADX instructions", "adx"),
FeatureInfo(@This()).createWithSubfeatures(.Aes, "aes", "Enable AES instructions", "aes", &[_]@This() {
.Sse,
}),
FeatureInfo(@This()).createWithSubfeatures(.Avx, "avx", "Enable AVX instructions", "avx", &[_]@This() {
.Sse,
}),
FeatureInfo(@This()).createWithSubfeatures(.Avx2, "avx2", "Enable AVX2 instructions", "avx2", &[_]@This() {
.Sse,
}),
FeatureInfo(@This()).createWithSubfeatures(.Avx512f, "avx512f", "Enable AVX-512 instructions", "avx512f", &[_]@This() {
.Sse,
}),
FeatureInfo(@This()).createWithSubfeatures(.Avx512bf16, "avx512bf16", "Support bfloat16 floating point", "avx512bf16", &[_]@This() {
.Sse,
}),
FeatureInfo(@This()).createWithSubfeatures(.Avx512bitalg, "avx512bitalg", "Enable AVX-512 Bit Algorithms", "avx512bitalg", &[_]@This() {
.Sse,
}),
FeatureInfo(@This()).create(.Bmi, "bmi", "Support BMI instructions", "bmi"),
FeatureInfo(@This()).create(.Bmi2, "bmi2", "Support BMI2 instructions", "bmi2"),
FeatureInfo(@This()).createWithSubfeatures(.Avx512bw, "avx512bw", "Enable AVX-512 Byte and Word Instructions", "avx512bw", &[_]@This() {
.Sse,
}),
FeatureInfo(@This()).create(.Branchfusion, "branchfusion", "CMP/TEST can be fused with conditional branches", "branchfusion"),
FeatureInfo(@This()).createWithSubfeatures(.Avx512cd, "avx512cd", "Enable AVX-512 Conflict Detection Instructions", "avx512cd", &[_]@This() {
.Sse,
}),
FeatureInfo(@This()).create(.Cldemote, "cldemote", "Enable Cache Demote", "cldemote"),
FeatureInfo(@This()).create(.Clflushopt, "clflushopt", "Flush A Cache Line Optimized", "clflushopt"),
FeatureInfo(@This()).create(.Clwb, "clwb", "Cache Line Write Back", "clwb"),
FeatureInfo(@This()).create(.Clzero, "clzero", "Enable Cache Line Zero", "clzero"),
FeatureInfo(@This()).create(.Cmov, "cmov", "Enable conditional move instructions", "cmov"),
FeatureInfo(@This()).create(.Cx8, "cx8", "Support CMPXCHG8B instructions", "cx8"),
FeatureInfo(@This()).createWithSubfeatures(.Cx16, "cx16", "64-bit with cmpxchg16b", "cx16", &[_]@This() {
.Cx8,
}),
FeatureInfo(@This()).createWithSubfeatures(.Avx512dq, "avx512dq", "Enable AVX-512 Doubleword and Quadword Instructions", "avx512dq", &[_]@This() {
.Sse,
}),
FeatureInfo(@This()).create(.Mpx, "mpx", "Deprecated. Support MPX instructions", "mpx"),
FeatureInfo(@This()).create(.Enqcmd, "enqcmd", "Has ENQCMD instructions", "enqcmd"),
FeatureInfo(@This()).createWithSubfeatures(.Avx512er, "avx512er", "Enable AVX-512 Exponential and Reciprocal Instructions", "avx512er", &[_]@This() {
.Sse,
}),
FeatureInfo(@This()).create(.Ermsb, "ermsb", "REP MOVS/STOS are fast", "ermsb"),
FeatureInfo(@This()).createWithSubfeatures(.F16c, "f16c", "Support 16-bit floating point conversion instructions", "f16c", &[_]@This() {
.Sse,
}),
FeatureInfo(@This()).createWithSubfeatures(.Fma, "fma", "Enable three-operand fused multiple-add", "fma", &[_]@This() {
.Sse,
}),
FeatureInfo(@This()).createWithSubfeatures(.Fma4, "fma4", "Enable four-operand fused multiple-add", "fma4", &[_]@This() {
.Sse,
}),
FeatureInfo(@This()).create(.Fsgsbase, "fsgsbase", "Support FS/GS Base instructions", "fsgsbase"),
FeatureInfo(@This()).create(.Fxsr, "fxsr", "Support fxsave/fxrestore instructions", "fxsr"),
FeatureInfo(@This()).create(.Fast11bytenop, "fast-11bytenop", "Target can quickly decode up to 11 byte NOPs", "fast-11bytenop"),
FeatureInfo(@This()).create(.Fast15bytenop, "fast-15bytenop", "Target can quickly decode up to 15 byte NOPs", "fast-15bytenop"),
FeatureInfo(@This()).create(.FastBextr, "fast-bextr", "Indicates that the BEXTR instruction is implemented as a single uop with good throughput", "fast-bextr"),
FeatureInfo(@This()).createWithSubfeatures(.FastHops, "fast-hops", "Prefer horizontal vector math instructions (haddp, phsub, etc.) over normal vector instructions with shuffles", "fast-hops", &[_]@This() {
.Sse,
}),
FeatureInfo(@This()).create(.FastLzcnt, "fast-lzcnt", "LZCNT instructions are as fast as most simple integer ops", "fast-lzcnt"),
FeatureInfo(@This()).create(.FastPartialYmmOrZmmWrite, "fast-partial-ymm-or-zmm-write", "Partial writes to YMM/ZMM registers are fast", "fast-partial-ymm-or-zmm-write"),
FeatureInfo(@This()).create(.FastShldRotate, "fast-shld-rotate", "SHLD can be used as a faster rotate", "fast-shld-rotate"),
FeatureInfo(@This()).create(.FastScalarFsqrt, "fast-scalar-fsqrt", "Scalar SQRT is fast (disable Newton-Raphson)", "fast-scalar-fsqrt"),
FeatureInfo(@This()).create(.FastScalarShiftMasks, "fast-scalar-shift-masks", "Prefer a left/right scalar logical shift pair over a shift+and pair", "fast-scalar-shift-masks"),
FeatureInfo(@This()).create(.FastVariableShuffle, "fast-variable-shuffle", "Shuffles with variable masks are fast", "fast-variable-shuffle"),
FeatureInfo(@This()).create(.FastVectorFsqrt, "fast-vector-fsqrt", "Vector SQRT is fast (disable Newton-Raphson)", "fast-vector-fsqrt"),
FeatureInfo(@This()).create(.FastVectorShiftMasks, "fast-vector-shift-masks", "Prefer a left/right vector logical shift pair over a shift+and pair", "fast-vector-shift-masks"),
FeatureInfo(@This()).createWithSubfeatures(.Gfni, "gfni", "Enable Galois Field Arithmetic Instructions", "gfni", &[_]@This() {
.Sse,
}),
FeatureInfo(@This()).create(.FastGather, "fast-gather", "Indicates if gather is reasonably fast", "fast-gather"),
FeatureInfo(@This()).createWithSubfeatures(.Avx512ifma, "avx512ifma", "Enable AVX-512 Integer Fused Multiple-Add", "avx512ifma", &[_]@This() {
.Sse,
}),
FeatureInfo(@This()).create(.Invpcid, "invpcid", "Invalidate Process-Context Identifier", "invpcid"),
FeatureInfo(@This()).create(.Sahf, "sahf", "Support LAHF and SAHF instructions", "sahf"),
FeatureInfo(@This()).create(.LeaSp, "lea-sp", "Use LEA for adjusting the stack pointer", "lea-sp"),
FeatureInfo(@This()).create(.LeaUsesAg, "lea-uses-ag", "LEA instruction needs inputs at AG stage", "lea-uses-ag"),
FeatureInfo(@This()).create(.Lwp, "lwp", "Enable LWP instructions", "lwp"),
FeatureInfo(@This()).create(.Lzcnt, "lzcnt", "Support LZCNT instruction", "lzcnt"),
FeatureInfo(@This()).create(.FalseDepsLzcntTzcnt, "false-deps-lzcnt-tzcnt", "LZCNT/TZCNT have a false dependency on dest register", "false-deps-lzcnt-tzcnt"),
FeatureInfo(@This()).create(.Mmx, "mmx", "Enable MMX instructions", "mmx"),
FeatureInfo(@This()).create(.Movbe, "movbe", "Support MOVBE instruction", "movbe"),
FeatureInfo(@This()).create(.Movdir64b, "movdir64b", "Support movdir64b instruction", "movdir64b"),
FeatureInfo(@This()).create(.Movdiri, "movdiri", "Support movdiri instruction", "movdiri"),
FeatureInfo(@This()).create(.Mwaitx, "mwaitx", "Enable MONITORX/MWAITX timer functionality", "mwaitx"),
FeatureInfo(@This()).create(.Macrofusion, "macrofusion", "Various instructions can be fused with conditional branches", "macrofusion"),
FeatureInfo(@This()).create(.MergeToThreewayBranch, "merge-to-threeway-branch", "Merge branches to a three-way conditional branch", "merge-to-threeway-branch"),
FeatureInfo(@This()).create(.Nopl, "nopl", "Enable NOPL instruction", "nopl"),
FeatureInfo(@This()).createWithSubfeatures(.Pclmul, "pclmul", "Enable packed carry-less multiplication instructions", "pclmul", &[_]@This() {
.Sse,
}),
FeatureInfo(@This()).create(.Pconfig, "pconfig", "platform configuration instruction", "pconfig"),
FeatureInfo(@This()).createWithSubfeatures(.Avx512pf, "avx512pf", "Enable AVX-512 PreFetch Instructions", "avx512pf", &[_]@This() {
.Sse,
}),
FeatureInfo(@This()).create(.Pku, "pku", "Enable protection keys", "pku"),
FeatureInfo(@This()).create(.Popcnt, "popcnt", "Support POPCNT instruction", "popcnt"),
FeatureInfo(@This()).create(.FalseDepsPopcnt, "false-deps-popcnt", "POPCNT has a false dependency on dest register", "false-deps-popcnt"),
FeatureInfo(@This()).create(.Prefetchwt1, "prefetchwt1", "Prefetch with Intent to Write and T1 Hint", "prefetchwt1"),
FeatureInfo(@This()).create(.Prfchw, "prfchw", "Support PRFCHW instructions", "prfchw"),
FeatureInfo(@This()).create(.Ptwrite, "ptwrite", "Support ptwrite instruction", "ptwrite"),
FeatureInfo(@This()).create(.PadShortFunctions, "pad-short-functions", "Pad short functions", "pad-short-functions"),
FeatureInfo(@This()).create(.Prefer128Bit, "prefer-128-bit", "Prefer 128-bit AVX instructions", "prefer-128-bit"),
FeatureInfo(@This()).create(.Prefer256Bit, "prefer-256-bit", "Prefer 256-bit AVX instructions", "prefer-256-bit"),
FeatureInfo(@This()).create(.Rdpid, "rdpid", "Support RDPID instructions", "rdpid"),
FeatureInfo(@This()).create(.Rdrnd, "rdrnd", "Support RDRAND instruction", "rdrnd"),
FeatureInfo(@This()).create(.Rdseed, "rdseed", "Support RDSEED instruction", "rdseed"),
FeatureInfo(@This()).create(.Rtm, "rtm", "Support RTM instructions", "rtm"),
FeatureInfo(@This()).createWithSubfeatures(.Retpoline, "retpoline", "Remove speculation of indirect branches from the generated code, either by avoiding them entirely or lowering them with a speculation blocking construct", "retpoline", &[_]@This() {
.RetpolineIndirectCalls,
.RetpolineIndirectBranches,
}),
FeatureInfo(@This()).createWithSubfeatures(.RetpolineExternalThunk, "retpoline-external-thunk", "When lowering an indirect call or branch using a `retpoline`, rely on the specified user provided thunk rather than emitting one ourselves. Only has effect when combined with some other retpoline feature", "retpoline-external-thunk", &[_]@This() {
.RetpolineIndirectCalls,
}),
FeatureInfo(@This()).create(.RetpolineIndirectBranches, "retpoline-indirect-branches", "Remove speculation of indirect branches from the generated code", "retpoline-indirect-branches"),
FeatureInfo(@This()).create(.RetpolineIndirectCalls, "retpoline-indirect-calls", "Remove speculation of indirect calls from the generated code", "retpoline-indirect-calls"),
FeatureInfo(@This()).create(.Sgx, "sgx", "Enable Software Guard Extensions", "sgx"),
FeatureInfo(@This()).createWithSubfeatures(.Sha, "sha", "Enable SHA instructions", "sha", &[_]@This() {
.Sse,
}),
FeatureInfo(@This()).create(.Shstk, "shstk", "Support CET Shadow-Stack instructions", "shstk"),
FeatureInfo(@This()).create(.Sse, "sse", "Enable SSE instructions", "sse"),
FeatureInfo(@This()).createWithSubfeatures(.Sse2, "sse2", "Enable SSE2 instructions", "sse2", &[_]@This() {
.Sse,
}),
FeatureInfo(@This()).createWithSubfeatures(.Sse3, "sse3", "Enable SSE3 instructions", "sse3", &[_]@This() {
.Sse,
}),
FeatureInfo(@This()).createWithSubfeatures(.Sse4a, "sse4a", "Support SSE 4a instructions", "sse4a", &[_]@This() {
.Sse,
}),
FeatureInfo(@This()).createWithSubfeatures(.Sse41, "sse4.1", "Enable SSE 4.1 instructions", "sse4.1", &[_]@This() {
.Sse,
}),
FeatureInfo(@This()).createWithSubfeatures(.Sse42, "sse4.2", "Enable SSE 4.2 instructions", "sse4.2", &[_]@This() {
.Sse,
}),
FeatureInfo(@This()).create(.SseUnalignedMem, "sse-unaligned-mem", "Allow unaligned memory operands with SSE instructions", "sse-unaligned-mem"),
FeatureInfo(@This()).createWithSubfeatures(.Ssse3, "ssse3", "Enable SSSE3 instructions", "ssse3", &[_]@This() {
.Sse,
}),
FeatureInfo(@This()).create(.Slow3opsLea, "slow-3ops-lea", "LEA instruction with 3 ops or certain registers is slow", "slow-3ops-lea"),
FeatureInfo(@This()).create(.IdivlToDivb, "idivl-to-divb", "Use 8-bit divide for positive values less than 256", "idivl-to-divb"),
FeatureInfo(@This()).create(.IdivqToDivl, "idivq-to-divl", "Use 32-bit divide for positive values less than 2^32", "idivq-to-divl"),
FeatureInfo(@This()).create(.SlowIncdec, "slow-incdec", "INC and DEC instructions are slower than ADD and SUB", "slow-incdec"),
FeatureInfo(@This()).create(.SlowLea, "slow-lea", "LEA instruction with certain arguments is slow", "slow-lea"),
FeatureInfo(@This()).create(.SlowPmaddwd, "slow-pmaddwd", "PMADDWD is slower than PMULLD", "slow-pmaddwd"),
FeatureInfo(@This()).create(.SlowPmulld, "slow-pmulld", "PMULLD instruction is slow", "slow-pmulld"),
FeatureInfo(@This()).create(.SlowShld, "slow-shld", "SHLD instruction is slow", "slow-shld"),
FeatureInfo(@This()).create(.SlowTwoMemOps, "slow-two-mem-ops", "Two memory operand instructions are slow", "slow-two-mem-ops"),
FeatureInfo(@This()).create(.SlowUnalignedMem16, "slow-unaligned-mem-16", "Slow unaligned 16-byte memory access", "slow-unaligned-mem-16"),
FeatureInfo(@This()).create(.SlowUnalignedMem32, "slow-unaligned-mem-32", "Slow unaligned 32-byte memory access", "slow-unaligned-mem-32"),
FeatureInfo(@This()).create(.SoftFloat, "soft-float", "Use software floating point features", "soft-float"),
FeatureInfo(@This()).create(.Tbm, "tbm", "Enable TBM instructions", "tbm"),
FeatureInfo(@This()).create(.UseAa, "use-aa", "Use alias analysis during codegen", "use-aa"),
FeatureInfo(@This()).createWithSubfeatures(.Vaes, "vaes", "Promote selected AES instructions to AVX512/AVX registers", "vaes", &[_]@This() {
.Sse,
}),
FeatureInfo(@This()).createWithSubfeatures(.Avx512vbmi, "avx512vbmi", "Enable AVX-512 Vector Byte Manipulation Instructions", "avx512vbmi", &[_]@This() {
.Sse,
}),
FeatureInfo(@This()).createWithSubfeatures(.Avx512vbmi2, "avx512vbmi2", "Enable AVX-512 further Vector Byte Manipulation Instructions", "avx512vbmi2", &[_]@This() {
.Sse,
}),
FeatureInfo(@This()).createWithSubfeatures(.Avx512vl, "avx512vl", "Enable AVX-512 Vector Length eXtensions", "avx512vl", &[_]@This() {
.Sse,
}),
FeatureInfo(@This()).createWithSubfeatures(.Avx512vnni, "avx512vnni", "Enable AVX-512 Vector Neural Network Instructions", "avx512vnni", &[_]@This() {
.Sse,
}),
FeatureInfo(@This()).createWithSubfeatures(.Avx512vp2intersect, "avx512vp2intersect", "Enable AVX-512 vp2intersect", "avx512vp2intersect", &[_]@This() {
.Sse,
}),
FeatureInfo(@This()).createWithSubfeatures(.Vpclmulqdq, "vpclmulqdq", "Enable vpclmulqdq instructions", "vpclmulqdq", &[_]@This() {
.Sse,
}),
FeatureInfo(@This()).createWithSubfeatures(.Avx512vpopcntdq, "avx512vpopcntdq", "Enable AVX-512 Population Count Instructions", "avx512vpopcntdq", &[_]@This() {
.Sse,
}),
FeatureInfo(@This()).create(.Waitpkg, "waitpkg", "Wait and pause enhancements", "waitpkg"),
FeatureInfo(@This()).create(.Wbnoinvd, "wbnoinvd", "Write Back No Invalidate", "wbnoinvd"),
FeatureInfo(@This()).create(.X87, "x87", "Enable X87 float instructions", "x87"),
FeatureInfo(@This()).createWithSubfeatures(.Xop, "xop", "Enable XOP instructions", "xop", &[_]@This() {
.Sse,
}),
FeatureInfo(@This()).create(.Xsave, "xsave", "Support xsave instructions", "xsave"),
FeatureInfo(@This()).create(.Xsavec, "xsavec", "Support xsavec instructions", "xsavec"),
FeatureInfo(@This()).create(.Xsaveopt, "xsaveopt", "Support xsaveopt instructions", "xsaveopt"),
FeatureInfo(@This()).create(.Xsaves, "xsaves", "Support xsaves instructions", "xsaves"),
FeatureInfo(@This()).create(.BitMode16, "16bit-mode", "16-bit mode (i8086)", "16bit-mode"),
FeatureInfo(@This()).create(.BitMode32, "32bit-mode", "32-bit mode (80386)", "32bit-mode"),
FeatureInfo(@This()).create(.BitMode64, "64bit-mode", "64-bit mode (x86_64)", "64bit-mode"),
};
};

5
lib/std/target/feature/empty.zig
View File

@@ -1,5 +0,0 @@
const FeatureInfo = @import("std").target.feature.FeatureInfo;
pub const EmptyFeature = struct {
pub const feature_infos = [0]FeatureInfo(@This()) {};
};

357
lib/std/target/hexagon.zig Normal file
View File

@@ -0,0 +1,357 @@
const Feature = @import("std").target.Feature;
const Cpu = @import("std").target.Cpu;
pub const feature_v5 = Feature{
.name = "v5",
.description = "Enable Hexagon V5 architecture",
.llvm_name = "v5",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_v55 = Feature{
.name = "v55",
.description = "Enable Hexagon V55 architecture",
.llvm_name = "v55",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_v60 = Feature{
.name = "v60",
.description = "Enable Hexagon V60 architecture",
.llvm_name = "v60",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_v62 = Feature{
.name = "v62",
.description = "Enable Hexagon V62 architecture",
.llvm_name = "v62",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_v65 = Feature{
.name = "v65",
.description = "Enable Hexagon V65 architecture",
.llvm_name = "v65",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_v66 = Feature{
.name = "v66",
.description = "Enable Hexagon V66 architecture",
.llvm_name = "v66",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_hvx = Feature{
.name = "hvx",
.description = "Hexagon HVX instructions",
.llvm_name = "hvx",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_hvxLength64b = Feature{
.name = "hvx-length64b",
.description = "Hexagon HVX 64B instructions",
.llvm_name = "hvx-length64b",
.subfeatures = &[_]*const Feature {
&feature_hvx,
},
};
pub const feature_hvxLength128b = Feature{
.name = "hvx-length128b",
.description = "Hexagon HVX 128B instructions",
.llvm_name = "hvx-length128b",
.subfeatures = &[_]*const Feature {
&feature_hvx,
},
};
pub const feature_hvxv60 = Feature{
.name = "hvxv60",
.description = "Hexagon HVX instructions",
.llvm_name = "hvxv60",
.subfeatures = &[_]*const Feature {
&feature_hvx,
},
};
pub const feature_hvxv62 = Feature{
.name = "hvxv62",
.description = "Hexagon HVX instructions",
.llvm_name = "hvxv62",
.subfeatures = &[_]*const Feature {
&feature_hvx,
},
};
pub const feature_hvxv65 = Feature{
.name = "hvxv65",
.description = "Hexagon HVX instructions",
.llvm_name = "hvxv65",
.subfeatures = &[_]*const Feature {
&feature_hvx,
},
};
pub const feature_hvxv66 = Feature{
.name = "hvxv66",
.description = "Hexagon HVX instructions",
.llvm_name = "hvxv66",
.subfeatures = &[_]*const Feature {
&feature_zreg,
&feature_hvx,
},
};
pub const feature_zreg = Feature{
.name = "zreg",
.description = "Hexagon ZReg extension instructions",
.llvm_name = "zreg",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_duplex = Feature{
.name = "duplex",
.description = "Enable generation of duplex instruction",
.llvm_name = "duplex",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_longCalls = Feature{
.name = "long-calls",
.description = "Use constant-extended calls",
.llvm_name = "long-calls",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_mem_noshuf = Feature{
.name = "mem_noshuf",
.description = "Supports mem_noshuf feature",
.llvm_name = "mem_noshuf",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_memops = Feature{
.name = "memops",
.description = "Use memop instructions",
.llvm_name = "memops",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_nvj = Feature{
.name = "nvj",
.description = "Support for new-value jumps",
.llvm_name = "nvj",
.subfeatures = &[_]*const Feature {
&feature_packets,
},
};
pub const feature_nvs = Feature{
.name = "nvs",
.description = "Support for new-value stores",
.llvm_name = "nvs",
.subfeatures = &[_]*const Feature {
&feature_packets,
},
};
pub const feature_noreturnStackElim = Feature{
.name = "noreturn-stack-elim",
.description = "Eliminate stack allocation in a noreturn function when possible",
.llvm_name = "noreturn-stack-elim",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_packets = Feature{
.name = "packets",
.description = "Support for instruction packets",
.llvm_name = "packets",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_reservedR19 = Feature{
.name = "reserved-r19",
.description = "Reserve register R19",
.llvm_name = "reserved-r19",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_smallData = Feature{
.name = "small-data",
.description = "Allow GP-relative addressing of global variables",
.llvm_name = "small-data",
.subfeatures = &[_]*const Feature {
},
};
pub const features = &[_]*const Feature {
&feature_v5,
&feature_v55,
&feature_v60,
&feature_v62,
&feature_v65,
&feature_v66,
&feature_hvx,
&feature_hvxLength64b,
&feature_hvxLength128b,
&feature_hvxv60,
&feature_hvxv62,
&feature_hvxv65,
&feature_hvxv66,
&feature_zreg,
&feature_duplex,
&feature_longCalls,
&feature_mem_noshuf,
&feature_memops,
&feature_nvj,
&feature_nvs,
&feature_noreturnStackElim,
&feature_packets,
&feature_reservedR19,
&feature_smallData,
};
pub const cpu_generic = Cpu{
.name = "generic",
.llvm_name = "generic",
.subfeatures = &[_]*const Feature {
&feature_v5,
&feature_v55,
&feature_v60,
&feature_duplex,
&feature_memops,
&feature_packets,
&feature_nvj,
&feature_nvs,
&feature_smallData,
},
};
pub const cpu_hexagonv5 = Cpu{
.name = "hexagonv5",
.llvm_name = "hexagonv5",
.subfeatures = &[_]*const Feature {
&feature_v5,
&feature_duplex,
&feature_memops,
&feature_packets,
&feature_nvj,
&feature_nvs,
&feature_smallData,
},
};
pub const cpu_hexagonv55 = Cpu{
.name = "hexagonv55",
.llvm_name = "hexagonv55",
.subfeatures = &[_]*const Feature {
&feature_v5,
&feature_v55,
&feature_duplex,
&feature_memops,
&feature_packets,
&feature_nvj,
&feature_nvs,
&feature_smallData,
},
};
pub const cpu_hexagonv60 = Cpu{
.name = "hexagonv60",
.llvm_name = "hexagonv60",
.subfeatures = &[_]*const Feature {
&feature_v5,
&feature_v55,
&feature_v60,
&feature_duplex,
&feature_memops,
&feature_packets,
&feature_nvj,
&feature_nvs,
&feature_smallData,
},
};
pub const cpu_hexagonv62 = Cpu{
.name = "hexagonv62",
.llvm_name = "hexagonv62",
.subfeatures = &[_]*const Feature {
&feature_v5,
&feature_v55,
&feature_v60,
&feature_v62,
&feature_duplex,
&feature_memops,
&feature_packets,
&feature_nvj,
&feature_nvs,
&feature_smallData,
},
};
pub const cpu_hexagonv65 = Cpu{
.name = "hexagonv65",
.llvm_name = "hexagonv65",
.subfeatures = &[_]*const Feature {
&feature_v5,
&feature_v55,
&feature_v60,
&feature_v62,
&feature_v65,
&feature_duplex,
&feature_mem_noshuf,
&feature_memops,
&feature_packets,
&feature_nvj,
&feature_nvs,
&feature_smallData,
},
};
pub const cpu_hexagonv66 = Cpu{
.name = "hexagonv66",
.llvm_name = "hexagonv66",
.subfeatures = &[_]*const Feature {
&feature_v5,
&feature_v55,
&feature_v60,
&feature_v62,
&feature_v65,
&feature_v66,
&feature_duplex,
&feature_mem_noshuf,
&feature_memops,
&feature_packets,
&feature_nvj,
&feature_nvs,
&feature_smallData,
},
};
pub const cpus = &[_]*const Cpu {
&cpu_generic,
&cpu_hexagonv5,
&cpu_hexagonv55,
&cpu_hexagonv60,
&cpu_hexagonv62,
&cpu_hexagonv65,
&cpu_hexagonv66,
};

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lib/std/target/mips.zig Normal file
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@@ -0,0 +1,828 @@
const Feature = @import("std").target.Feature;
const Cpu = @import("std").target.Cpu;
pub const feature_abs2008 = Feature{
.name = "abs2008",
.description = "Disable IEEE 754-2008 abs.fmt mode",
.llvm_name = "abs2008",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_crc = Feature{
.name = "crc",
.description = "Mips R6 CRC ASE",
.llvm_name = "crc",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_cnmips = Feature{
.name = "cnmips",
.description = "Octeon cnMIPS Support",
.llvm_name = "cnmips",
.subfeatures = &[_]*const Feature {
&feature_mips4_32,
&feature_mips3_32r2,
&feature_mips1,
&feature_gp64,
&feature_mips4_32r2,
&feature_mips5_32r2,
&feature_mips3_32,
&feature_fp64,
},
};
pub const feature_dsp = Feature{
.name = "dsp",
.description = "Mips DSP ASE",
.llvm_name = "dsp",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_dspr2 = Feature{
.name = "dspr2",
.description = "Mips DSP-R2 ASE",
.llvm_name = "dspr2",
.subfeatures = &[_]*const Feature {
&feature_dsp,
},
};
pub const feature_dspr3 = Feature{
.name = "dspr3",
.description = "Mips DSP-R3 ASE",
.llvm_name = "dspr3",
.subfeatures = &[_]*const Feature {
&feature_dsp,
},
};
pub const feature_eva = Feature{
.name = "eva",
.description = "Mips EVA ASE",
.llvm_name = "eva",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_fp64 = Feature{
.name = "fp64",
.description = "Support 64-bit FP registers",
.llvm_name = "fp64",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_fpxx = Feature{
.name = "fpxx",
.description = "Support for FPXX",
.llvm_name = "fpxx",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_ginv = Feature{
.name = "ginv",
.description = "Mips Global Invalidate ASE",
.llvm_name = "ginv",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_gp64 = Feature{
.name = "gp64",
.description = "General Purpose Registers are 64-bit wide",
.llvm_name = "gp64",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_longCalls = Feature{
.name = "long-calls",
.description = "Disable use of the jal instruction",
.llvm_name = "long-calls",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_msa = Feature{
.name = "msa",
.description = "Mips MSA ASE",
.llvm_name = "msa",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_mt = Feature{
.name = "mt",
.description = "Mips MT ASE",
.llvm_name = "mt",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_nomadd4 = Feature{
.name = "nomadd4",
.description = "Disable 4-operand madd.fmt and related instructions",
.llvm_name = "nomadd4",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_micromips = Feature{
.name = "micromips",
.description = "microMips mode",
.llvm_name = "micromips",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_mips1 = Feature{
.name = "mips1",
.description = "Mips I ISA Support [highly experimental]",
.llvm_name = "mips1",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_mips2 = Feature{
.name = "mips2",
.description = "Mips II ISA Support [highly experimental]",
.llvm_name = "mips2",
.subfeatures = &[_]*const Feature {
&feature_mips1,
},
};
pub const feature_mips3 = Feature{
.name = "mips3",
.description = "MIPS III ISA Support [highly experimental]",
.llvm_name = "mips3",
.subfeatures = &[_]*const Feature {
&feature_mips3_32r2,
&feature_mips1,
&feature_gp64,
&feature_mips3_32,
&feature_fp64,
},
};
pub const feature_mips3_32 = Feature{
.name = "mips3_32",
.description = "Subset of MIPS-III that is also in MIPS32 [highly experimental]",
.llvm_name = "mips3_32",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_mips3_32r2 = Feature{
.name = "mips3_32r2",
.description = "Subset of MIPS-III that is also in MIPS32r2 [highly experimental]",
.llvm_name = "mips3_32r2",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_mips4 = Feature{
.name = "mips4",
.description = "MIPS IV ISA Support",
.llvm_name = "mips4",
.subfeatures = &[_]*const Feature {
&feature_mips4_32,
&feature_mips3_32r2,
&feature_mips1,
&feature_gp64,
&feature_mips4_32r2,
&feature_mips3_32,
&feature_fp64,
},
};
pub const feature_mips4_32 = Feature{
.name = "mips4_32",
.description = "Subset of MIPS-IV that is also in MIPS32 [highly experimental]",
.llvm_name = "mips4_32",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_mips4_32r2 = Feature{
.name = "mips4_32r2",
.description = "Subset of MIPS-IV that is also in MIPS32r2 [highly experimental]",
.llvm_name = "mips4_32r2",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_mips5 = Feature{
.name = "mips5",
.description = "MIPS V ISA Support [highly experimental]",
.llvm_name = "mips5",
.subfeatures = &[_]*const Feature {
&feature_mips4_32,
&feature_mips3_32r2,
&feature_mips1,
&feature_gp64,
&feature_mips4_32r2,
&feature_mips5_32r2,
&feature_mips3_32,
&feature_fp64,
},
};
pub const feature_mips5_32r2 = Feature{
.name = "mips5_32r2",
.description = "Subset of MIPS-V that is also in MIPS32r2 [highly experimental]",
.llvm_name = "mips5_32r2",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_mips16 = Feature{
.name = "mips16",
.description = "Mips16 mode",
.llvm_name = "mips16",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_mips32 = Feature{
.name = "mips32",
.description = "Mips32 ISA Support",
.llvm_name = "mips32",
.subfeatures = &[_]*const Feature {
&feature_mips4_32,
&feature_mips3_32,
&feature_mips1,
},
};
pub const feature_mips32r2 = Feature{
.name = "mips32r2",
.description = "Mips32r2 ISA Support",
.llvm_name = "mips32r2",
.subfeatures = &[_]*const Feature {
&feature_mips4_32,
&feature_mips3_32r2,
&feature_mips1,
&feature_mips4_32r2,
&feature_mips5_32r2,
&feature_mips3_32,
},
};
pub const feature_mips32r3 = Feature{
.name = "mips32r3",
.description = "Mips32r3 ISA Support",
.llvm_name = "mips32r3",
.subfeatures = &[_]*const Feature {
&feature_mips4_32,
&feature_mips3_32r2,
&feature_mips1,
&feature_mips4_32r2,
&feature_mips5_32r2,
&feature_mips3_32,
},
};
pub const feature_mips32r5 = Feature{
.name = "mips32r5",
.description = "Mips32r5 ISA Support",
.llvm_name = "mips32r5",
.subfeatures = &[_]*const Feature {
&feature_mips4_32,
&feature_mips3_32r2,
&feature_mips1,
&feature_mips4_32r2,
&feature_mips5_32r2,
&feature_mips3_32,
},
};
pub const feature_mips32r6 = Feature{
.name = "mips32r6",
.description = "Mips32r6 ISA Support [experimental]",
.llvm_name = "mips32r6",
.subfeatures = &[_]*const Feature {
&feature_mips4_32,
&feature_nan2008,
&feature_mips3_32r2,
&feature_mips1,
&feature_abs2008,
&feature_mips4_32r2,
&feature_mips5_32r2,
&feature_mips3_32,
&feature_fp64,
},
};
pub const feature_mips64 = Feature{
.name = "mips64",
.description = "Mips64 ISA Support",
.llvm_name = "mips64",
.subfeatures = &[_]*const Feature {
&feature_mips4_32,
&feature_mips3_32r2,
&feature_mips1,
&feature_gp64,
&feature_mips4_32r2,
&feature_mips5_32r2,
&feature_mips3_32,
&feature_fp64,
},
};
pub const feature_mips64r2 = Feature{
.name = "mips64r2",
.description = "Mips64r2 ISA Support",
.llvm_name = "mips64r2",
.subfeatures = &[_]*const Feature {
&feature_mips4_32,
&feature_mips3_32r2,
&feature_mips1,
&feature_gp64,
&feature_mips4_32r2,
&feature_mips5_32r2,
&feature_mips3_32,
&feature_fp64,
},
};
pub const feature_mips64r3 = Feature{
.name = "mips64r3",
.description = "Mips64r3 ISA Support",
.llvm_name = "mips64r3",
.subfeatures = &[_]*const Feature {
&feature_mips4_32,
&feature_mips3_32r2,
&feature_mips1,
&feature_gp64,
&feature_mips4_32r2,
&feature_mips5_32r2,
&feature_mips3_32,
&feature_fp64,
},
};
pub const feature_mips64r5 = Feature{
.name = "mips64r5",
.description = "Mips64r5 ISA Support",
.llvm_name = "mips64r5",
.subfeatures = &[_]*const Feature {
&feature_mips4_32,
&feature_mips3_32r2,
&feature_mips1,
&feature_gp64,
&feature_mips4_32r2,
&feature_mips5_32r2,
&feature_mips3_32,
&feature_fp64,
},
};
pub const feature_mips64r6 = Feature{
.name = "mips64r6",
.description = "Mips64r6 ISA Support [experimental]",
.llvm_name = "mips64r6",
.subfeatures = &[_]*const Feature {
&feature_mips4_32,
&feature_nan2008,
&feature_mips3_32r2,
&feature_mips1,
&feature_abs2008,
&feature_gp64,
&feature_mips4_32r2,
&feature_mips5_32r2,
&feature_mips3_32,
&feature_fp64,
},
};
pub const feature_nan2008 = Feature{
.name = "nan2008",
.description = "IEEE 754-2008 NaN encoding",
.llvm_name = "nan2008",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_noabicalls = Feature{
.name = "noabicalls",
.description = "Disable SVR4-style position-independent code",
.llvm_name = "noabicalls",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_nooddspreg = Feature{
.name = "nooddspreg",
.description = "Disable odd numbered single-precision registers",
.llvm_name = "nooddspreg",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_ptr64 = Feature{
.name = "ptr64",
.description = "Pointers are 64-bit wide",
.llvm_name = "ptr64",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_singleFloat = Feature{
.name = "single-float",
.description = "Only supports single precision float",
.llvm_name = "single-float",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_softFloat = Feature{
.name = "soft-float",
.description = "Does not support floating point instructions",
.llvm_name = "soft-float",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_sym32 = Feature{
.name = "sym32",
.description = "Symbols are 32 bit on Mips64",
.llvm_name = "sym32",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_useIndirectJumpHazard = Feature{
.name = "use-indirect-jump-hazard",
.description = "Use indirect jump guards to prevent certain speculation based attacks",
.llvm_name = "use-indirect-jump-hazard",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_useTccInDiv = Feature{
.name = "use-tcc-in-div",
.description = "Force the assembler to use trapping",
.llvm_name = "use-tcc-in-div",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_vfpu = Feature{
.name = "vfpu",
.description = "Enable vector FPU instructions",
.llvm_name = "vfpu",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_virt = Feature{
.name = "virt",
.description = "Mips Virtualization ASE",
.llvm_name = "virt",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_xgot = Feature{
.name = "xgot",
.description = "Assume 32-bit GOT",
.llvm_name = "xgot",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_p5600 = Feature{
.name = "p5600",
.description = "The P5600 Processor",
.llvm_name = "p5600",
.subfeatures = &[_]*const Feature {
&feature_mips4_32,
&feature_mips3_32r2,
&feature_mips1,
&feature_mips4_32r2,
&feature_mips5_32r2,
&feature_mips3_32,
},
};
pub const features = &[_]*const Feature {
&feature_abs2008,
&feature_crc,
&feature_cnmips,
&feature_dsp,
&feature_dspr2,
&feature_dspr3,
&feature_eva,
&feature_fp64,
&feature_fpxx,
&feature_ginv,
&feature_gp64,
&feature_longCalls,
&feature_msa,
&feature_mt,
&feature_nomadd4,
&feature_micromips,
&feature_mips1,
&feature_mips2,
&feature_mips3,
&feature_mips3_32,
&feature_mips3_32r2,
&feature_mips4,
&feature_mips4_32,
&feature_mips4_32r2,
&feature_mips5,
&feature_mips5_32r2,
&feature_mips16,
&feature_mips32,
&feature_mips32r2,
&feature_mips32r3,
&feature_mips32r5,
&feature_mips32r6,
&feature_mips64,
&feature_mips64r2,
&feature_mips64r3,
&feature_mips64r5,
&feature_mips64r6,
&feature_nan2008,
&feature_noabicalls,
&feature_nooddspreg,
&feature_ptr64,
&feature_singleFloat,
&feature_softFloat,
&feature_sym32,
&feature_useIndirectJumpHazard,
&feature_useTccInDiv,
&feature_vfpu,
&feature_virt,
&feature_xgot,
&feature_p5600,
};
pub const cpu_mips1 = Cpu{
.name = "mips1",
.llvm_name = "mips1",
.subfeatures = &[_]*const Feature {
&feature_mips1,
},
};
pub const cpu_mips2 = Cpu{
.name = "mips2",
.llvm_name = "mips2",
.subfeatures = &[_]*const Feature {
&feature_mips1,
&feature_mips2,
},
};
pub const cpu_mips3 = Cpu{
.name = "mips3",
.llvm_name = "mips3",
.subfeatures = &[_]*const Feature {
&feature_mips3_32r2,
&feature_mips1,
&feature_gp64,
&feature_mips3_32,
&feature_fp64,
&feature_mips3,
},
};
pub const cpu_mips32 = Cpu{
.name = "mips32",
.llvm_name = "mips32",
.subfeatures = &[_]*const Feature {
&feature_mips4_32,
&feature_mips3_32,
&feature_mips1,
&feature_mips32,
},
};
pub const cpu_mips32r2 = Cpu{
.name = "mips32r2",
.llvm_name = "mips32r2",
.subfeatures = &[_]*const Feature {
&feature_mips4_32,
&feature_mips3_32r2,
&feature_mips1,
&feature_mips4_32r2,
&feature_mips5_32r2,
&feature_mips3_32,
&feature_mips32r2,
},
};
pub const cpu_mips32r3 = Cpu{
.name = "mips32r3",
.llvm_name = "mips32r3",
.subfeatures = &[_]*const Feature {
&feature_mips4_32,
&feature_mips3_32r2,
&feature_mips1,
&feature_mips4_32r2,
&feature_mips5_32r2,
&feature_mips3_32,
&feature_mips32r3,
},
};
pub const cpu_mips32r5 = Cpu{
.name = "mips32r5",
.llvm_name = "mips32r5",
.subfeatures = &[_]*const Feature {
&feature_mips4_32,
&feature_mips3_32r2,
&feature_mips1,
&feature_mips4_32r2,
&feature_mips5_32r2,
&feature_mips3_32,
&feature_mips32r5,
},
};
pub const cpu_mips32r6 = Cpu{
.name = "mips32r6",
.llvm_name = "mips32r6",
.subfeatures = &[_]*const Feature {
&feature_mips4_32,
&feature_nan2008,
&feature_mips3_32r2,
&feature_mips1,
&feature_abs2008,
&feature_mips4_32r2,
&feature_mips5_32r2,
&feature_mips3_32,
&feature_fp64,
&feature_mips32r6,
},
};
pub const cpu_mips4 = Cpu{
.name = "mips4",
.llvm_name = "mips4",
.subfeatures = &[_]*const Feature {
&feature_mips4_32,
&feature_mips3_32r2,
&feature_mips1,
&feature_gp64,
&feature_mips4_32r2,
&feature_mips3_32,
&feature_fp64,
&feature_mips4,
},
};
pub const cpu_mips5 = Cpu{
.name = "mips5",
.llvm_name = "mips5",
.subfeatures = &[_]*const Feature {
&feature_mips4_32,
&feature_mips3_32r2,
&feature_mips1,
&feature_gp64,
&feature_mips4_32r2,
&feature_mips5_32r2,
&feature_mips3_32,
&feature_fp64,
&feature_mips5,
},
};
pub const cpu_mips64 = Cpu{
.name = "mips64",
.llvm_name = "mips64",
.subfeatures = &[_]*const Feature {
&feature_mips4_32,
&feature_mips3_32r2,
&feature_mips1,
&feature_gp64,
&feature_mips4_32r2,
&feature_mips5_32r2,
&feature_mips3_32,
&feature_fp64,
&feature_mips64,
},
};
pub const cpu_mips64r2 = Cpu{
.name = "mips64r2",
.llvm_name = "mips64r2",
.subfeatures = &[_]*const Feature {
&feature_mips4_32,
&feature_mips3_32r2,
&feature_mips1,
&feature_gp64,
&feature_mips4_32r2,
&feature_mips5_32r2,
&feature_mips3_32,
&feature_fp64,
&feature_mips64r2,
},
};
pub const cpu_mips64r3 = Cpu{
.name = "mips64r3",
.llvm_name = "mips64r3",
.subfeatures = &[_]*const Feature {
&feature_mips4_32,
&feature_mips3_32r2,
&feature_mips1,
&feature_gp64,
&feature_mips4_32r2,
&feature_mips5_32r2,
&feature_mips3_32,
&feature_fp64,
&feature_mips64r3,
},
};
pub const cpu_mips64r5 = Cpu{
.name = "mips64r5",
.llvm_name = "mips64r5",
.subfeatures = &[_]*const Feature {
&feature_mips4_32,
&feature_mips3_32r2,
&feature_mips1,
&feature_gp64,
&feature_mips4_32r2,
&feature_mips5_32r2,
&feature_mips3_32,
&feature_fp64,
&feature_mips64r5,
},
};
pub const cpu_mips64r6 = Cpu{
.name = "mips64r6",
.llvm_name = "mips64r6",
.subfeatures = &[_]*const Feature {
&feature_mips4_32,
&feature_nan2008,
&feature_mips3_32r2,
&feature_mips1,
&feature_abs2008,
&feature_gp64,
&feature_mips4_32r2,
&feature_mips5_32r2,
&feature_mips3_32,
&feature_fp64,
&feature_mips64r6,
},
};
pub const cpu_octeon = Cpu{
.name = "octeon",
.llvm_name = "octeon",
.subfeatures = &[_]*const Feature {
&feature_mips4_32,
&feature_mips3_32r2,
&feature_mips1,
&feature_gp64,
&feature_mips4_32r2,
&feature_mips5_32r2,
&feature_mips3_32,
&feature_fp64,
&feature_cnmips,
&feature_mips64r2,
},
};
pub const cpu_p5600 = Cpu{
.name = "p5600",
.llvm_name = "p5600",
.subfeatures = &[_]*const Feature {
&feature_mips4_32,
&feature_mips3_32r2,
&feature_mips1,
&feature_mips4_32r2,
&feature_mips5_32r2,
&feature_mips3_32,
&feature_p5600,
},
};
pub const cpus = &[_]*const Cpu {
&cpu_mips1,
&cpu_mips2,
&cpu_mips3,
&cpu_mips32,
&cpu_mips32r2,
&cpu_mips32r3,
&cpu_mips32r5,
&cpu_mips32r6,
&cpu_mips4,
&cpu_mips5,
&cpu_mips64,
&cpu_mips64r2,
&cpu_mips64r3,
&cpu_mips64r5,
&cpu_mips64r6,
&cpu_octeon,
&cpu_p5600,
};

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lib/std/target/msp430.zig Normal file
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const Feature = @import("std").target.Feature;
const Cpu = @import("std").target.Cpu;
pub const feature_hwmult16 = Feature{
.name = "hwmult16",
.description = "Enable 16-bit hardware multiplier",
.llvm_name = "hwmult16",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_hwmult32 = Feature{
.name = "hwmult32",
.description = "Enable 32-bit hardware multiplier",
.llvm_name = "hwmult32",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_hwmultf5 = Feature{
.name = "hwmultf5",
.description = "Enable F5 series hardware multiplier",
.llvm_name = "hwmultf5",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_ext = Feature{
.name = "ext",
.description = "Enable MSP430-X extensions",
.llvm_name = "ext",
.subfeatures = &[_]*const Feature {
},
};
pub const features = &[_]*const Feature {
&feature_hwmult16,
&feature_hwmult32,
&feature_hwmultf5,
&feature_ext,
};
pub const cpu_generic = Cpu{
.name = "generic",
.llvm_name = "generic",
.subfeatures = &[_]*const Feature {
},
};
pub const cpu_msp430 = Cpu{
.name = "msp430",
.llvm_name = "msp430",
.subfeatures = &[_]*const Feature {
},
};
pub const cpu_msp430x = Cpu{
.name = "msp430x",
.llvm_name = "msp430x",
.subfeatures = &[_]*const Feature {
&feature_ext,
},
};
pub const cpus = &[_]*const Cpu {
&cpu_generic,
&cpu_msp430,
&cpu_msp430x,
};

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const Feature = @import("std").target.Feature;
const Cpu = @import("std").target.Cpu;
pub const feature_ptx32 = Feature{
.name = "ptx32",
.description = "Use PTX version 3.2",
.llvm_name = "ptx32",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_ptx40 = Feature{
.name = "ptx40",
.description = "Use PTX version 4.0",
.llvm_name = "ptx40",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_ptx41 = Feature{
.name = "ptx41",
.description = "Use PTX version 4.1",
.llvm_name = "ptx41",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_ptx42 = Feature{
.name = "ptx42",
.description = "Use PTX version 4.2",
.llvm_name = "ptx42",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_ptx43 = Feature{
.name = "ptx43",
.description = "Use PTX version 4.3",
.llvm_name = "ptx43",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_ptx50 = Feature{
.name = "ptx50",
.description = "Use PTX version 5.0",
.llvm_name = "ptx50",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_ptx60 = Feature{
.name = "ptx60",
.description = "Use PTX version 6.0",
.llvm_name = "ptx60",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_ptx61 = Feature{
.name = "ptx61",
.description = "Use PTX version 6.1",
.llvm_name = "ptx61",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_ptx63 = Feature{
.name = "ptx63",
.description = "Use PTX version 6.3",
.llvm_name = "ptx63",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_ptx64 = Feature{
.name = "ptx64",
.description = "Use PTX version 6.4",
.llvm_name = "ptx64",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_sm_20 = Feature{
.name = "sm_20",
.description = "Target SM 2.0",
.llvm_name = "sm_20",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_sm_21 = Feature{
.name = "sm_21",
.description = "Target SM 2.1",
.llvm_name = "sm_21",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_sm_30 = Feature{
.name = "sm_30",
.description = "Target SM 3.0",
.llvm_name = "sm_30",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_sm_32 = Feature{
.name = "sm_32",
.description = "Target SM 3.2",
.llvm_name = "sm_32",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_sm_35 = Feature{
.name = "sm_35",
.description = "Target SM 3.5",
.llvm_name = "sm_35",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_sm_37 = Feature{
.name = "sm_37",
.description = "Target SM 3.7",
.llvm_name = "sm_37",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_sm_50 = Feature{
.name = "sm_50",
.description = "Target SM 5.0",
.llvm_name = "sm_50",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_sm_52 = Feature{
.name = "sm_52",
.description = "Target SM 5.2",
.llvm_name = "sm_52",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_sm_53 = Feature{
.name = "sm_53",
.description = "Target SM 5.3",
.llvm_name = "sm_53",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_sm_60 = Feature{
.name = "sm_60",
.description = "Target SM 6.0",
.llvm_name = "sm_60",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_sm_61 = Feature{
.name = "sm_61",
.description = "Target SM 6.1",
.llvm_name = "sm_61",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_sm_62 = Feature{
.name = "sm_62",
.description = "Target SM 6.2",
.llvm_name = "sm_62",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_sm_70 = Feature{
.name = "sm_70",
.description = "Target SM 7.0",
.llvm_name = "sm_70",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_sm_72 = Feature{
.name = "sm_72",
.description = "Target SM 7.2",
.llvm_name = "sm_72",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_sm_75 = Feature{
.name = "sm_75",
.description = "Target SM 7.5",
.llvm_name = "sm_75",
.subfeatures = &[_]*const Feature {
},
};
pub const features = &[_]*const Feature {
&feature_ptx32,
&feature_ptx40,
&feature_ptx41,
&feature_ptx42,
&feature_ptx43,
&feature_ptx50,
&feature_ptx60,
&feature_ptx61,
&feature_ptx63,
&feature_ptx64,
&feature_sm_20,
&feature_sm_21,
&feature_sm_30,
&feature_sm_32,
&feature_sm_35,
&feature_sm_37,
&feature_sm_50,
&feature_sm_52,
&feature_sm_53,
&feature_sm_60,
&feature_sm_61,
&feature_sm_62,
&feature_sm_70,
&feature_sm_72,
&feature_sm_75,
};
pub const cpu_sm_20 = Cpu{
.name = "sm_20",
.llvm_name = "sm_20",
.subfeatures = &[_]*const Feature {
&feature_sm_20,
},
};
pub const cpu_sm_21 = Cpu{
.name = "sm_21",
.llvm_name = "sm_21",
.subfeatures = &[_]*const Feature {
&feature_sm_21,
},
};
pub const cpu_sm_30 = Cpu{
.name = "sm_30",
.llvm_name = "sm_30",
.subfeatures = &[_]*const Feature {
&feature_sm_30,
},
};
pub const cpu_sm_32 = Cpu{
.name = "sm_32",
.llvm_name = "sm_32",
.subfeatures = &[_]*const Feature {
&feature_ptx40,
&feature_sm_32,
},
};
pub const cpu_sm_35 = Cpu{
.name = "sm_35",
.llvm_name = "sm_35",
.subfeatures = &[_]*const Feature {
&feature_sm_35,
},
};
pub const cpu_sm_37 = Cpu{
.name = "sm_37",
.llvm_name = "sm_37",
.subfeatures = &[_]*const Feature {
&feature_ptx41,
&feature_sm_37,
},
};
pub const cpu_sm_50 = Cpu{
.name = "sm_50",
.llvm_name = "sm_50",
.subfeatures = &[_]*const Feature {
&feature_ptx40,
&feature_sm_50,
},
};
pub const cpu_sm_52 = Cpu{
.name = "sm_52",
.llvm_name = "sm_52",
.subfeatures = &[_]*const Feature {
&feature_ptx41,
&feature_sm_52,
},
};
pub const cpu_sm_53 = Cpu{
.name = "sm_53",
.llvm_name = "sm_53",
.subfeatures = &[_]*const Feature {
&feature_ptx42,
&feature_sm_53,
},
};
pub const cpu_sm_60 = Cpu{
.name = "sm_60",
.llvm_name = "sm_60",
.subfeatures = &[_]*const Feature {
&feature_ptx50,
&feature_sm_60,
},
};
pub const cpu_sm_61 = Cpu{
.name = "sm_61",
.llvm_name = "sm_61",
.subfeatures = &[_]*const Feature {
&feature_ptx50,
&feature_sm_61,
},
};
pub const cpu_sm_62 = Cpu{
.name = "sm_62",
.llvm_name = "sm_62",
.subfeatures = &[_]*const Feature {
&feature_ptx50,
&feature_sm_62,
},
};
pub const cpu_sm_70 = Cpu{
.name = "sm_70",
.llvm_name = "sm_70",
.subfeatures = &[_]*const Feature {
&feature_ptx60,
&feature_sm_70,
},
};
pub const cpu_sm_72 = Cpu{
.name = "sm_72",
.llvm_name = "sm_72",
.subfeatures = &[_]*const Feature {
&feature_ptx61,
&feature_sm_72,
},
};
pub const cpu_sm_75 = Cpu{
.name = "sm_75",
.llvm_name = "sm_75",
.subfeatures = &[_]*const Feature {
&feature_ptx63,
&feature_sm_75,
},
};
pub const cpus = &[_]*const Cpu {
&cpu_sm_20,
&cpu_sm_21,
&cpu_sm_30,
&cpu_sm_32,
&cpu_sm_35,
&cpu_sm_37,
&cpu_sm_50,
&cpu_sm_52,
&cpu_sm_53,
&cpu_sm_60,
&cpu_sm_61,
&cpu_sm_62,
&cpu_sm_70,
&cpu_sm_72,
&cpu_sm_75,
};

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lib/std/target/riscv.zig Normal file
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const Feature = @import("std").target.Feature;
const Cpu = @import("std").target.Cpu;
pub const feature_bit64 = Feature{
.name = "64bit",
.description = "Implements RV64",
.llvm_name = "64bit",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_e = Feature{
.name = "e",
.description = "Implements RV32E (provides 16 rather than 32 GPRs)",
.llvm_name = "e",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_rvcHints = Feature{
.name = "rvc-hints",
.description = "Enable RVC Hint Instructions.",
.llvm_name = "rvc-hints",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_relax = Feature{
.name = "relax",
.description = "Enable Linker relaxation.",
.llvm_name = "relax",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_a = Feature{
.name = "a",
.description = "'A' (Atomic Instructions)",
.llvm_name = "a",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_c = Feature{
.name = "c",
.description = "'C' (Compressed Instructions)",
.llvm_name = "c",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_d = Feature{
.name = "d",
.description = "'D' (Double-Precision Floating-Point)",
.llvm_name = "d",
.subfeatures = &[_]*const Feature {
&feature_f,
},
};
pub const feature_f = Feature{
.name = "f",
.description = "'F' (Single-Precision Floating-Point)",
.llvm_name = "f",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_m = Feature{
.name = "m",
.description = "'M' (Integer Multiplication and Division)",
.llvm_name = "m",
.subfeatures = &[_]*const Feature {
},
};
pub const features = &[_]*const Feature {
&feature_bit64,
&feature_e,
&feature_rvcHints,
&feature_relax,
&feature_a,
&feature_c,
&feature_d,
&feature_f,
&feature_m,
};
pub const cpu_genericRv32 = Cpu{
.name = "generic-rv32",
.llvm_name = "generic-rv32",
.subfeatures = &[_]*const Feature {
&feature_rvcHints,
},
};
pub const cpu_genericRv64 = Cpu{
.name = "generic-rv64",
.llvm_name = "generic-rv64",
.subfeatures = &[_]*const Feature {
&feature_bit64,
&feature_rvcHints,
},
};
pub const cpus = &[_]*const Cpu {
&cpu_genericRv32,
&cpu_genericRv64,
};

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const Feature = @import("std").target.Feature;
const Cpu = @import("std").target.Cpu;
pub const feature_detectroundchange = Feature{
.name = "detectroundchange",
.description = "LEON3 erratum detection: Detects any rounding mode change request: use only the round-to-nearest rounding mode",
.llvm_name = "detectroundchange",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_hardQuadFloat = Feature{
.name = "hard-quad-float",
.description = "Enable quad-word floating point instructions",
.llvm_name = "hard-quad-float",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_leon = Feature{
.name = "leon",
.description = "Enable LEON extensions",
.llvm_name = "leon",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_noFmuls = Feature{
.name = "no-fmuls",
.description = "Disable the fmuls instruction.",
.llvm_name = "no-fmuls",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_noFsmuld = Feature{
.name = "no-fsmuld",
.description = "Disable the fsmuld instruction.",
.llvm_name = "no-fsmuld",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_leonpwrpsr = Feature{
.name = "leonpwrpsr",
.description = "Enable the PWRPSR instruction",
.llvm_name = "leonpwrpsr",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_softFloat = Feature{
.name = "soft-float",
.description = "Use software emulation for floating point",
.llvm_name = "soft-float",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_softMulDiv = Feature{
.name = "soft-mul-div",
.description = "Use software emulation for integer multiply and divide",
.llvm_name = "soft-mul-div",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_deprecatedV8 = Feature{
.name = "deprecated-v8",
.description = "Enable deprecated V8 instructions in V9 mode",
.llvm_name = "deprecated-v8",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_v9 = Feature{
.name = "v9",
.description = "Enable SPARC-V9 instructions",
.llvm_name = "v9",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_vis = Feature{
.name = "vis",
.description = "Enable UltraSPARC Visual Instruction Set extensions",
.llvm_name = "vis",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_vis2 = Feature{
.name = "vis2",
.description = "Enable Visual Instruction Set extensions II",
.llvm_name = "vis2",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_vis3 = Feature{
.name = "vis3",
.description = "Enable Visual Instruction Set extensions III",
.llvm_name = "vis3",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_fixallfdivsqrt = Feature{
.name = "fixallfdivsqrt",
.description = "LEON erratum fix: Fix FDIVS/FDIVD/FSQRTS/FSQRTD instructions with NOPs and floating-point store",
.llvm_name = "fixallfdivsqrt",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_insertnopload = Feature{
.name = "insertnopload",
.description = "LEON3 erratum fix: Insert a NOP instruction after every single-cycle load instruction when the next instruction is another load/store instruction",
.llvm_name = "insertnopload",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_hasleoncasa = Feature{
.name = "hasleoncasa",
.description = "Enable CASA instruction for LEON3 and LEON4 processors",
.llvm_name = "hasleoncasa",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_leoncyclecounter = Feature{
.name = "leoncyclecounter",
.description = "Use the Leon cycle counter register",
.llvm_name = "leoncyclecounter",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_hasumacsmac = Feature{
.name = "hasumacsmac",
.description = "Enable UMAC and SMAC for LEON3 and LEON4 processors",
.llvm_name = "hasumacsmac",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_popc = Feature{
.name = "popc",
.description = "Use the popc (population count) instruction",
.llvm_name = "popc",
.subfeatures = &[_]*const Feature {
},
};
pub const features = &[_]*const Feature {
&feature_detectroundchange,
&feature_hardQuadFloat,
&feature_leon,
&feature_noFmuls,
&feature_noFsmuld,
&feature_leonpwrpsr,
&feature_softFloat,
&feature_softMulDiv,
&feature_deprecatedV8,
&feature_v9,
&feature_vis,
&feature_vis2,
&feature_vis3,
&feature_fixallfdivsqrt,
&feature_insertnopload,
&feature_hasleoncasa,
&feature_leoncyclecounter,
&feature_hasumacsmac,
&feature_popc,
};
pub const cpu_at697e = Cpu{
.name = "at697e",
.llvm_name = "at697e",
.subfeatures = &[_]*const Feature {
&feature_leon,
&feature_insertnopload,
},
};
pub const cpu_at697f = Cpu{
.name = "at697f",
.llvm_name = "at697f",
.subfeatures = &[_]*const Feature {
&feature_leon,
&feature_insertnopload,
},
};
pub const cpu_f934 = Cpu{
.name = "f934",
.llvm_name = "f934",
.subfeatures = &[_]*const Feature {
},
};
pub const cpu_generic = Cpu{
.name = "generic",
.llvm_name = "generic",
.subfeatures = &[_]*const Feature {
},
};
pub const cpu_gr712rc = Cpu{
.name = "gr712rc",
.llvm_name = "gr712rc",
.subfeatures = &[_]*const Feature {
&feature_leon,
&feature_hasleoncasa,
},
};
pub const cpu_gr740 = Cpu{
.name = "gr740",
.llvm_name = "gr740",
.subfeatures = &[_]*const Feature {
&feature_leon,
&feature_leonpwrpsr,
&feature_hasleoncasa,
&feature_leoncyclecounter,
&feature_hasumacsmac,
},
};
pub const cpu_hypersparc = Cpu{
.name = "hypersparc",
.llvm_name = "hypersparc",
.subfeatures = &[_]*const Feature {
},
};
pub const cpu_leon2 = Cpu{
.name = "leon2",
.llvm_name = "leon2",
.subfeatures = &[_]*const Feature {
&feature_leon,
},
};
pub const cpu_leon3 = Cpu{
.name = "leon3",
.llvm_name = "leon3",
.subfeatures = &[_]*const Feature {
&feature_leon,
&feature_hasumacsmac,
},
};
pub const cpu_leon4 = Cpu{
.name = "leon4",
.llvm_name = "leon4",
.subfeatures = &[_]*const Feature {
&feature_leon,
&feature_hasleoncasa,
&feature_hasumacsmac,
},
};
pub const cpu_ma2080 = Cpu{
.name = "ma2080",
.llvm_name = "ma2080",
.subfeatures = &[_]*const Feature {
&feature_leon,
&feature_hasleoncasa,
},
};
pub const cpu_ma2085 = Cpu{
.name = "ma2085",
.llvm_name = "ma2085",
.subfeatures = &[_]*const Feature {
&feature_leon,
&feature_hasleoncasa,
},
};
pub const cpu_ma2100 = Cpu{
.name = "ma2100",
.llvm_name = "ma2100",
.subfeatures = &[_]*const Feature {
&feature_leon,
&feature_hasleoncasa,
},
};
pub const cpu_ma2150 = Cpu{
.name = "ma2150",
.llvm_name = "ma2150",
.subfeatures = &[_]*const Feature {
&feature_leon,
&feature_hasleoncasa,
},
};
pub const cpu_ma2155 = Cpu{
.name = "ma2155",
.llvm_name = "ma2155",
.subfeatures = &[_]*const Feature {
&feature_leon,
&feature_hasleoncasa,
},
};
pub const cpu_ma2450 = Cpu{
.name = "ma2450",
.llvm_name = "ma2450",
.subfeatures = &[_]*const Feature {
&feature_leon,
&feature_hasleoncasa,
},
};
pub const cpu_ma2455 = Cpu{
.name = "ma2455",
.llvm_name = "ma2455",
.subfeatures = &[_]*const Feature {
&feature_leon,
&feature_hasleoncasa,
},
};
pub const cpu_ma2480 = Cpu{
.name = "ma2480",
.llvm_name = "ma2480",
.subfeatures = &[_]*const Feature {
&feature_leon,
&feature_hasleoncasa,
},
};
pub const cpu_ma2485 = Cpu{
.name = "ma2485",
.llvm_name = "ma2485",
.subfeatures = &[_]*const Feature {
&feature_leon,
&feature_hasleoncasa,
},
};
pub const cpu_ma2x5x = Cpu{
.name = "ma2x5x",
.llvm_name = "ma2x5x",
.subfeatures = &[_]*const Feature {
&feature_leon,
&feature_hasleoncasa,
},
};
pub const cpu_ma2x8x = Cpu{
.name = "ma2x8x",
.llvm_name = "ma2x8x",
.subfeatures = &[_]*const Feature {
&feature_leon,
&feature_hasleoncasa,
},
};
pub const cpu_myriad2 = Cpu{
.name = "myriad2",
.llvm_name = "myriad2",
.subfeatures = &[_]*const Feature {
&feature_leon,
&feature_hasleoncasa,
},
};
pub const cpu_myriad21 = Cpu{
.name = "myriad2.1",
.llvm_name = "myriad2.1",
.subfeatures = &[_]*const Feature {
&feature_leon,
&feature_hasleoncasa,
},
};
pub const cpu_myriad22 = Cpu{
.name = "myriad2.2",
.llvm_name = "myriad2.2",
.subfeatures = &[_]*const Feature {
&feature_leon,
&feature_hasleoncasa,
},
};
pub const cpu_myriad23 = Cpu{
.name = "myriad2.3",
.llvm_name = "myriad2.3",
.subfeatures = &[_]*const Feature {
&feature_leon,
&feature_hasleoncasa,
},
};
pub const cpu_niagara = Cpu{
.name = "niagara",
.llvm_name = "niagara",
.subfeatures = &[_]*const Feature {
&feature_deprecatedV8,
&feature_v9,
&feature_vis,
&feature_vis2,
},
};
pub const cpu_niagara2 = Cpu{
.name = "niagara2",
.llvm_name = "niagara2",
.subfeatures = &[_]*const Feature {
&feature_deprecatedV8,
&feature_v9,
&feature_vis,
&feature_vis2,
&feature_popc,
},
};
pub const cpu_niagara3 = Cpu{
.name = "niagara3",
.llvm_name = "niagara3",
.subfeatures = &[_]*const Feature {
&feature_deprecatedV8,
&feature_v9,
&feature_vis,
&feature_vis2,
&feature_popc,
},
};
pub const cpu_niagara4 = Cpu{
.name = "niagara4",
.llvm_name = "niagara4",
.subfeatures = &[_]*const Feature {
&feature_deprecatedV8,
&feature_v9,
&feature_vis,
&feature_vis2,
&feature_vis3,
&feature_popc,
},
};
pub const cpu_sparclet = Cpu{
.name = "sparclet",
.llvm_name = "sparclet",
.subfeatures = &[_]*const Feature {
},
};
pub const cpu_sparclite = Cpu{
.name = "sparclite",
.llvm_name = "sparclite",
.subfeatures = &[_]*const Feature {
},
};
pub const cpu_sparclite86x = Cpu{
.name = "sparclite86x",
.llvm_name = "sparclite86x",
.subfeatures = &[_]*const Feature {
},
};
pub const cpu_supersparc = Cpu{
.name = "supersparc",
.llvm_name = "supersparc",
.subfeatures = &[_]*const Feature {
},
};
pub const cpu_tsc701 = Cpu{
.name = "tsc701",
.llvm_name = "tsc701",
.subfeatures = &[_]*const Feature {
},
};
pub const cpu_ultrasparc = Cpu{
.name = "ultrasparc",
.llvm_name = "ultrasparc",
.subfeatures = &[_]*const Feature {
&feature_deprecatedV8,
&feature_v9,
&feature_vis,
},
};
pub const cpu_ultrasparc3 = Cpu{
.name = "ultrasparc3",
.llvm_name = "ultrasparc3",
.subfeatures = &[_]*const Feature {
&feature_deprecatedV8,
&feature_v9,
&feature_vis,
&feature_vis2,
},
};
pub const cpu_ut699 = Cpu{
.name = "ut699",
.llvm_name = "ut699",
.subfeatures = &[_]*const Feature {
&feature_leon,
&feature_noFmuls,
&feature_noFsmuld,
&feature_fixallfdivsqrt,
&feature_insertnopload,
},
};
pub const cpu_v7 = Cpu{
.name = "v7",
.llvm_name = "v7",
.subfeatures = &[_]*const Feature {
&feature_noFsmuld,
&feature_softMulDiv,
},
};
pub const cpu_v8 = Cpu{
.name = "v8",
.llvm_name = "v8",
.subfeatures = &[_]*const Feature {
},
};
pub const cpu_v9 = Cpu{
.name = "v9",
.llvm_name = "v9",
.subfeatures = &[_]*const Feature {
&feature_v9,
},
};
pub const cpus = &[_]*const Cpu {
&cpu_at697e,
&cpu_at697f,
&cpu_f934,
&cpu_generic,
&cpu_gr712rc,
&cpu_gr740,
&cpu_hypersparc,
&cpu_leon2,
&cpu_leon3,
&cpu_leon4,
&cpu_ma2080,
&cpu_ma2085,
&cpu_ma2100,
&cpu_ma2150,
&cpu_ma2155,
&cpu_ma2450,
&cpu_ma2455,
&cpu_ma2480,
&cpu_ma2485,
&cpu_ma2x5x,
&cpu_ma2x8x,
&cpu_myriad2,
&cpu_myriad21,
&cpu_myriad22,
&cpu_myriad23,
&cpu_niagara,
&cpu_niagara2,
&cpu_niagara3,
&cpu_niagara4,
&cpu_sparclet,
&cpu_sparclite,
&cpu_sparclite86x,
&cpu_supersparc,
&cpu_tsc701,
&cpu_ultrasparc,
&cpu_ultrasparc3,
&cpu_ut699,
&cpu_v7,
&cpu_v8,
&cpu_v9,
};

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const Feature = @import("std").target.Feature;
const Cpu = @import("std").target.Cpu;
pub const feature_dfpPackedConversion = Feature{
.name = "dfp-packed-conversion",
.description = "Assume that the DFP packed-conversion facility is installed",
.llvm_name = "dfp-packed-conversion",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_dfpZonedConversion = Feature{
.name = "dfp-zoned-conversion",
.description = "Assume that the DFP zoned-conversion facility is installed",
.llvm_name = "dfp-zoned-conversion",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_deflateConversion = Feature{
.name = "deflate-conversion",
.description = "Assume that the deflate-conversion facility is installed",
.llvm_name = "deflate-conversion",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_distinctOps = Feature{
.name = "distinct-ops",
.description = "Assume that the distinct-operands facility is installed",
.llvm_name = "distinct-ops",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_enhancedDat2 = Feature{
.name = "enhanced-dat-2",
.description = "Assume that the enhanced-DAT facility 2 is installed",
.llvm_name = "enhanced-dat-2",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_enhancedSort = Feature{
.name = "enhanced-sort",
.description = "Assume that the enhanced-sort facility is installed",
.llvm_name = "enhanced-sort",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_executionHint = Feature{
.name = "execution-hint",
.description = "Assume that the execution-hint facility is installed",
.llvm_name = "execution-hint",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_fpExtension = Feature{
.name = "fp-extension",
.description = "Assume that the floating-point extension facility is installed",
.llvm_name = "fp-extension",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_fastSerialization = Feature{
.name = "fast-serialization",
.description = "Assume that the fast-serialization facility is installed",
.llvm_name = "fast-serialization",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_guardedStorage = Feature{
.name = "guarded-storage",
.description = "Assume that the guarded-storage facility is installed",
.llvm_name = "guarded-storage",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_highWord = Feature{
.name = "high-word",
.description = "Assume that the high-word facility is installed",
.llvm_name = "high-word",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_insertReferenceBitsMultiple = Feature{
.name = "insert-reference-bits-multiple",
.description = "Assume that the insert-reference-bits-multiple facility is installed",
.llvm_name = "insert-reference-bits-multiple",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_interlockedAccess1 = Feature{
.name = "interlocked-access1",
.description = "Assume that interlocked-access facility 1 is installed",
.llvm_name = "interlocked-access1",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_loadAndTrap = Feature{
.name = "load-and-trap",
.description = "Assume that the load-and-trap facility is installed",
.llvm_name = "load-and-trap",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_loadAndZeroRightmostByte = Feature{
.name = "load-and-zero-rightmost-byte",
.description = "Assume that the load-and-zero-rightmost-byte facility is installed",
.llvm_name = "load-and-zero-rightmost-byte",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_loadStoreOnCond = Feature{
.name = "load-store-on-cond",
.description = "Assume that the load/store-on-condition facility is installed",
.llvm_name = "load-store-on-cond",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_loadStoreOnCond2 = Feature{
.name = "load-store-on-cond-2",
.description = "Assume that the load/store-on-condition facility 2 is installed",
.llvm_name = "load-store-on-cond-2",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_messageSecurityAssistExtension3 = Feature{
.name = "message-security-assist-extension3",
.description = "Assume that the message-security-assist extension facility 3 is installed",
.llvm_name = "message-security-assist-extension3",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_messageSecurityAssistExtension4 = Feature{
.name = "message-security-assist-extension4",
.description = "Assume that the message-security-assist extension facility 4 is installed",
.llvm_name = "message-security-assist-extension4",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_messageSecurityAssistExtension5 = Feature{
.name = "message-security-assist-extension5",
.description = "Assume that the message-security-assist extension facility 5 is installed",
.llvm_name = "message-security-assist-extension5",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_messageSecurityAssistExtension7 = Feature{
.name = "message-security-assist-extension7",
.description = "Assume that the message-security-assist extension facility 7 is installed",
.llvm_name = "message-security-assist-extension7",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_messageSecurityAssistExtension8 = Feature{
.name = "message-security-assist-extension8",
.description = "Assume that the message-security-assist extension facility 8 is installed",
.llvm_name = "message-security-assist-extension8",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_messageSecurityAssistExtension9 = Feature{
.name = "message-security-assist-extension9",
.description = "Assume that the message-security-assist extension facility 9 is installed",
.llvm_name = "message-security-assist-extension9",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_miscellaneousExtensions = Feature{
.name = "miscellaneous-extensions",
.description = "Assume that the miscellaneous-extensions facility is installed",
.llvm_name = "miscellaneous-extensions",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_miscellaneousExtensions2 = Feature{
.name = "miscellaneous-extensions-2",
.description = "Assume that the miscellaneous-extensions facility 2 is installed",
.llvm_name = "miscellaneous-extensions-2",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_miscellaneousExtensions3 = Feature{
.name = "miscellaneous-extensions-3",
.description = "Assume that the miscellaneous-extensions facility 3 is installed",
.llvm_name = "miscellaneous-extensions-3",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_populationCount = Feature{
.name = "population-count",
.description = "Assume that the population-count facility is installed",
.llvm_name = "population-count",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_processorAssist = Feature{
.name = "processor-assist",
.description = "Assume that the processor-assist facility is installed",
.llvm_name = "processor-assist",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_resetReferenceBitsMultiple = Feature{
.name = "reset-reference-bits-multiple",
.description = "Assume that the reset-reference-bits-multiple facility is installed",
.llvm_name = "reset-reference-bits-multiple",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_transactionalExecution = Feature{
.name = "transactional-execution",
.description = "Assume that the transactional-execution facility is installed",
.llvm_name = "transactional-execution",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_vector = Feature{
.name = "vector",
.description = "Assume that the vectory facility is installed",
.llvm_name = "vector",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_vectorEnhancements1 = Feature{
.name = "vector-enhancements-1",
.description = "Assume that the vector enhancements facility 1 is installed",
.llvm_name = "vector-enhancements-1",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_vectorEnhancements2 = Feature{
.name = "vector-enhancements-2",
.description = "Assume that the vector enhancements facility 2 is installed",
.llvm_name = "vector-enhancements-2",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_vectorPackedDecimal = Feature{
.name = "vector-packed-decimal",
.description = "Assume that the vector packed decimal facility is installed",
.llvm_name = "vector-packed-decimal",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_vectorPackedDecimalEnhancement = Feature{
.name = "vector-packed-decimal-enhancement",
.description = "Assume that the vector packed decimal enhancement facility is installed",
.llvm_name = "vector-packed-decimal-enhancement",
.subfeatures = &[_]*const Feature {
},
};
pub const features = &[_]*const Feature {
&feature_dfpPackedConversion,
&feature_dfpZonedConversion,
&feature_deflateConversion,
&feature_distinctOps,
&feature_enhancedDat2,
&feature_enhancedSort,
&feature_executionHint,
&feature_fpExtension,
&feature_fastSerialization,
&feature_guardedStorage,
&feature_highWord,
&feature_insertReferenceBitsMultiple,
&feature_interlockedAccess1,
&feature_loadAndTrap,
&feature_loadAndZeroRightmostByte,
&feature_loadStoreOnCond,
&feature_loadStoreOnCond2,
&feature_messageSecurityAssistExtension3,
&feature_messageSecurityAssistExtension4,
&feature_messageSecurityAssistExtension5,
&feature_messageSecurityAssistExtension7,
&feature_messageSecurityAssistExtension8,
&feature_messageSecurityAssistExtension9,
&feature_miscellaneousExtensions,
&feature_miscellaneousExtensions2,
&feature_miscellaneousExtensions3,
&feature_populationCount,
&feature_processorAssist,
&feature_resetReferenceBitsMultiple,
&feature_transactionalExecution,
&feature_vector,
&feature_vectorEnhancements1,
&feature_vectorEnhancements2,
&feature_vectorPackedDecimal,
&feature_vectorPackedDecimalEnhancement,
};
pub const cpu_arch10 = Cpu{
.name = "arch10",
.llvm_name = "arch10",
.subfeatures = &[_]*const Feature {
&feature_dfpZonedConversion,
&feature_distinctOps,
&feature_enhancedDat2,
&feature_executionHint,
&feature_fpExtension,
&feature_fastSerialization,
&feature_highWord,
&feature_interlockedAccess1,
&feature_loadAndTrap,
&feature_loadStoreOnCond,
&feature_messageSecurityAssistExtension3,
&feature_messageSecurityAssistExtension4,
&feature_miscellaneousExtensions,
&feature_populationCount,
&feature_processorAssist,
&feature_resetReferenceBitsMultiple,
&feature_transactionalExecution,
},
};
pub const cpu_arch11 = Cpu{
.name = "arch11",
.llvm_name = "arch11",
.subfeatures = &[_]*const Feature {
&feature_dfpPackedConversion,
&feature_dfpZonedConversion,
&feature_distinctOps,
&feature_enhancedDat2,
&feature_executionHint,
&feature_fpExtension,
&feature_fastSerialization,
&feature_highWord,
&feature_interlockedAccess1,
&feature_loadAndTrap,
&feature_loadAndZeroRightmostByte,
&feature_loadStoreOnCond,
&feature_loadStoreOnCond2,
&feature_messageSecurityAssistExtension3,
&feature_messageSecurityAssistExtension4,
&feature_messageSecurityAssistExtension5,
&feature_miscellaneousExtensions,
&feature_populationCount,
&feature_processorAssist,
&feature_resetReferenceBitsMultiple,
&feature_transactionalExecution,
&feature_vector,
},
};
pub const cpu_arch12 = Cpu{
.name = "arch12",
.llvm_name = "arch12",
.subfeatures = &[_]*const Feature {
&feature_dfpPackedConversion,
&feature_dfpZonedConversion,
&feature_distinctOps,
&feature_enhancedDat2,
&feature_executionHint,
&feature_fpExtension,
&feature_fastSerialization,
&feature_guardedStorage,
&feature_highWord,
&feature_insertReferenceBitsMultiple,
&feature_interlockedAccess1,
&feature_loadAndTrap,
&feature_loadAndZeroRightmostByte,
&feature_loadStoreOnCond,
&feature_loadStoreOnCond2,
&feature_messageSecurityAssistExtension3,
&feature_messageSecurityAssistExtension4,
&feature_messageSecurityAssistExtension5,
&feature_messageSecurityAssistExtension7,
&feature_messageSecurityAssistExtension8,
&feature_miscellaneousExtensions,
&feature_miscellaneousExtensions2,
&feature_populationCount,
&feature_processorAssist,
&feature_resetReferenceBitsMultiple,
&feature_transactionalExecution,
&feature_vector,
&feature_vectorEnhancements1,
&feature_vectorPackedDecimal,
},
};
pub const cpu_arch13 = Cpu{
.name = "arch13",
.llvm_name = "arch13",
.subfeatures = &[_]*const Feature {
&feature_dfpPackedConversion,
&feature_dfpZonedConversion,
&feature_deflateConversion,
&feature_distinctOps,
&feature_enhancedDat2,
&feature_enhancedSort,
&feature_executionHint,
&feature_fpExtension,
&feature_fastSerialization,
&feature_guardedStorage,
&feature_highWord,
&feature_insertReferenceBitsMultiple,
&feature_interlockedAccess1,
&feature_loadAndTrap,
&feature_loadAndZeroRightmostByte,
&feature_loadStoreOnCond,
&feature_loadStoreOnCond2,
&feature_messageSecurityAssistExtension3,
&feature_messageSecurityAssistExtension4,
&feature_messageSecurityAssistExtension5,
&feature_messageSecurityAssistExtension7,
&feature_messageSecurityAssistExtension8,
&feature_messageSecurityAssistExtension9,
&feature_miscellaneousExtensions,
&feature_miscellaneousExtensions2,
&feature_miscellaneousExtensions3,
&feature_populationCount,
&feature_processorAssist,
&feature_resetReferenceBitsMultiple,
&feature_transactionalExecution,
&feature_vector,
&feature_vectorEnhancements1,
&feature_vectorEnhancements2,
&feature_vectorPackedDecimal,
&feature_vectorPackedDecimalEnhancement,
},
};
pub const cpu_arch8 = Cpu{
.name = "arch8",
.llvm_name = "arch8",
.subfeatures = &[_]*const Feature {
},
};
pub const cpu_arch9 = Cpu{
.name = "arch9",
.llvm_name = "arch9",
.subfeatures = &[_]*const Feature {
&feature_distinctOps,
&feature_fpExtension,
&feature_fastSerialization,
&feature_highWord,
&feature_interlockedAccess1,
&feature_loadStoreOnCond,
&feature_messageSecurityAssistExtension3,
&feature_messageSecurityAssistExtension4,
&feature_populationCount,
&feature_resetReferenceBitsMultiple,
},
};
pub const cpu_generic = Cpu{
.name = "generic",
.llvm_name = "generic",
.subfeatures = &[_]*const Feature {
},
};
pub const cpu_z10 = Cpu{
.name = "z10",
.llvm_name = "z10",
.subfeatures = &[_]*const Feature {
},
};
pub const cpu_z13 = Cpu{
.name = "z13",
.llvm_name = "z13",
.subfeatures = &[_]*const Feature {
&feature_dfpPackedConversion,
&feature_dfpZonedConversion,
&feature_distinctOps,
&feature_enhancedDat2,
&feature_executionHint,
&feature_fpExtension,
&feature_fastSerialization,
&feature_highWord,
&feature_interlockedAccess1,
&feature_loadAndTrap,
&feature_loadAndZeroRightmostByte,
&feature_loadStoreOnCond,
&feature_loadStoreOnCond2,
&feature_messageSecurityAssistExtension3,
&feature_messageSecurityAssistExtension4,
&feature_messageSecurityAssistExtension5,
&feature_miscellaneousExtensions,
&feature_populationCount,
&feature_processorAssist,
&feature_resetReferenceBitsMultiple,
&feature_transactionalExecution,
&feature_vector,
},
};
pub const cpu_z14 = Cpu{
.name = "z14",
.llvm_name = "z14",
.subfeatures = &[_]*const Feature {
&feature_dfpPackedConversion,
&feature_dfpZonedConversion,
&feature_distinctOps,
&feature_enhancedDat2,
&feature_executionHint,
&feature_fpExtension,
&feature_fastSerialization,
&feature_guardedStorage,
&feature_highWord,
&feature_insertReferenceBitsMultiple,
&feature_interlockedAccess1,
&feature_loadAndTrap,
&feature_loadAndZeroRightmostByte,
&feature_loadStoreOnCond,
&feature_loadStoreOnCond2,
&feature_messageSecurityAssistExtension3,
&feature_messageSecurityAssistExtension4,
&feature_messageSecurityAssistExtension5,
&feature_messageSecurityAssistExtension7,
&feature_messageSecurityAssistExtension8,
&feature_miscellaneousExtensions,
&feature_miscellaneousExtensions2,
&feature_populationCount,
&feature_processorAssist,
&feature_resetReferenceBitsMultiple,
&feature_transactionalExecution,
&feature_vector,
&feature_vectorEnhancements1,
&feature_vectorPackedDecimal,
},
};
pub const cpu_z15 = Cpu{
.name = "z15",
.llvm_name = "z15",
.subfeatures = &[_]*const Feature {
&feature_dfpPackedConversion,
&feature_dfpZonedConversion,
&feature_deflateConversion,
&feature_distinctOps,
&feature_enhancedDat2,
&feature_enhancedSort,
&feature_executionHint,
&feature_fpExtension,
&feature_fastSerialization,
&feature_guardedStorage,
&feature_highWord,
&feature_insertReferenceBitsMultiple,
&feature_interlockedAccess1,
&feature_loadAndTrap,
&feature_loadAndZeroRightmostByte,
&feature_loadStoreOnCond,
&feature_loadStoreOnCond2,
&feature_messageSecurityAssistExtension3,
&feature_messageSecurityAssistExtension4,
&feature_messageSecurityAssistExtension5,
&feature_messageSecurityAssistExtension7,
&feature_messageSecurityAssistExtension8,
&feature_messageSecurityAssistExtension9,
&feature_miscellaneousExtensions,
&feature_miscellaneousExtensions2,
&feature_miscellaneousExtensions3,
&feature_populationCount,
&feature_processorAssist,
&feature_resetReferenceBitsMultiple,
&feature_transactionalExecution,
&feature_vector,
&feature_vectorEnhancements1,
&feature_vectorEnhancements2,
&feature_vectorPackedDecimal,
&feature_vectorPackedDecimalEnhancement,
},
};
pub const cpu_z196 = Cpu{
.name = "z196",
.llvm_name = "z196",
.subfeatures = &[_]*const Feature {
&feature_distinctOps,
&feature_fpExtension,
&feature_fastSerialization,
&feature_highWord,
&feature_interlockedAccess1,
&feature_loadStoreOnCond,
&feature_messageSecurityAssistExtension3,
&feature_messageSecurityAssistExtension4,
&feature_populationCount,
&feature_resetReferenceBitsMultiple,
},
};
pub const cpu_zEC12 = Cpu{
.name = "zEC12",
.llvm_name = "zEC12",
.subfeatures = &[_]*const Feature {
&feature_dfpZonedConversion,
&feature_distinctOps,
&feature_enhancedDat2,
&feature_executionHint,
&feature_fpExtension,
&feature_fastSerialization,
&feature_highWord,
&feature_interlockedAccess1,
&feature_loadAndTrap,
&feature_loadStoreOnCond,
&feature_messageSecurityAssistExtension3,
&feature_messageSecurityAssistExtension4,
&feature_miscellaneousExtensions,
&feature_populationCount,
&feature_processorAssist,
&feature_resetReferenceBitsMultiple,
&feature_transactionalExecution,
},
};
pub const cpus = &[_]*const Cpu {
&cpu_arch10,
&cpu_arch11,
&cpu_arch12,
&cpu_arch13,
&cpu_arch8,
&cpu_arch9,
&cpu_generic,
&cpu_z10,
&cpu_z13,
&cpu_z14,
&cpu_z15,
&cpu_z196,
&cpu_zEC12,
};

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const Feature = @import("std").target.Feature;
const Cpu = @import("std").target.Cpu;
pub const feature_atomics = Feature{
.name = "atomics",
.description = "Enable Atomics",
.llvm_name = "atomics",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_bulkMemory = Feature{
.name = "bulk-memory",
.description = "Enable bulk memory operations",
.llvm_name = "bulk-memory",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_exceptionHandling = Feature{
.name = "exception-handling",
.description = "Enable Wasm exception handling",
.llvm_name = "exception-handling",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_multivalue = Feature{
.name = "multivalue",
.description = "Enable multivalue blocks, instructions, and functions",
.llvm_name = "multivalue",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_mutableGlobals = Feature{
.name = "mutable-globals",
.description = "Enable mutable globals",
.llvm_name = "mutable-globals",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_nontrappingFptoint = Feature{
.name = "nontrapping-fptoint",
.description = "Enable non-trapping float-to-int conversion operators",
.llvm_name = "nontrapping-fptoint",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_simd128 = Feature{
.name = "simd128",
.description = "Enable 128-bit SIMD",
.llvm_name = "simd128",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_signExt = Feature{
.name = "sign-ext",
.description = "Enable sign extension operators",
.llvm_name = "sign-ext",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_tailCall = Feature{
.name = "tail-call",
.description = "Enable tail call instructions",
.llvm_name = "tail-call",
.subfeatures = &[_]*const Feature {
},
};
pub const feature_unimplementedSimd128 = Feature{
.name = "unimplemented-simd128",
.description = "Enable 128-bit SIMD not yet implemented in engines",
.llvm_name = "unimplemented-simd128",
.subfeatures = &[_]*const Feature {
&feature_simd128,
},
};
pub const features = &[_]*const Feature {
&feature_atomics,
&feature_bulkMemory,
&feature_exceptionHandling,
&feature_multivalue,
&feature_mutableGlobals,
&feature_nontrappingFptoint,
&feature_simd128,
&feature_signExt,
&feature_tailCall,
&feature_unimplementedSimd128,
};
pub const cpu_bleedingEdge = Cpu{
.name = "bleeding-edge",
.llvm_name = "bleeding-edge",
.subfeatures = &[_]*const Feature {
&feature_atomics,
&feature_mutableGlobals,
&feature_nontrappingFptoint,
&feature_simd128,
&feature_signExt,
},
};
pub const cpu_generic = Cpu{
.name = "generic",
.llvm_name = "generic",
.subfeatures = &[_]*const Feature {
},
};
pub const cpu_mvp = Cpu{
.name = "mvp",
.llvm_name = "mvp",
.subfeatures = &[_]*const Feature {
},
};
pub const cpus = &[_]*const Cpu {
&cpu_bleedingEdge,
&cpu_generic,
&cpu_mvp,
};

3427
lib/std/target/x86.zig Normal file
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88
src-self-hosted/stage1.zig
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@@ -6,8 +6,6 @@ const io = std.io;
const mem = std.mem;
const fs = std.fs;
const process = std.process;
const feature = std.target.feature;
const cpu = std.target.cpu;
const Allocator = mem.Allocator;
const ArrayList = std.ArrayList;
const Buffer = std.Buffer;
@@ -546,34 +544,30 @@ fn print_features_for_arch(arch_name: []const u8, show_subfeatures: bool) !void
return;
};
inline for (@typeInfo(@TagType(Target.Arch)).Enum.fields) |arch_enum_field| {
if (@enumToInt(arch) == arch_enum_field.value) {
const enum_arch = @intToEnum(@TagType(Target.Arch), arch_enum_field.value);
try stdout_stream.print("Available features for {}:\n", .{ @tagName(arch) });
const feature_infos = feature.ArchFeature(enum_arch).feature_infos;
const features = std.target.getFeaturesForArch(arch);
try stdout_stream.print("Available features for {}:\n", .{ arch_enum_field.name });
var longest_len: usize = 0;
for (features) |feature| {
if (feature.name.len > longest_len) {
longest_len = feature.name.len;
}
}
var longest_len: usize = 0;
for (feature_infos) |feature_info| {
if (feature_info.name.len > longest_len) longest_len = feature_info.name.len;
}
for (features) |feature| {
try stdout_stream.print(" {}", .{ feature.name });
var i: usize = 0;
while (i < longest_len - feature.name.len) : (i += 1) {
try stdout_stream.write(" ");
}
for (feature_infos) |feature_info| {
try stdout_stream.print(" {}", .{ feature_info.name });
var i: usize = 0;
while (i < longest_len - feature_info.name.len) : (i += 1) {
try stdout_stream.write(" ");
}
try stdout_stream.print(" - {}\n", .{ feature.description });
try stdout_stream.print(" - {}\n", .{ feature_info.description });
if (show_subfeatures and feature_info.subfeatures.len > 0) {
for (feature_info.subfeatures) |subfeature| {
try stdout_stream.print(" {}\n", .{ subfeature.getInfo().name });
}
}
if (show_subfeatures and feature.subfeatures.len > 0) {
for (feature.subfeatures) |subfeature| {
try stdout_stream.print(" {}\n", .{ subfeature.name });
}
}
}
@@ -594,35 +588,33 @@ fn print_cpus_for_arch(arch_name: []const u8, show_subfeatures: bool) !void {
return;
};
inline for (@typeInfo(@TagType(Target.Arch)).Enum.fields) |arch_enum_field| {
if (@enumToInt(arch) == arch_enum_field.value) {
const enum_arch = @intToEnum(@TagType(Target.Arch), arch_enum_field.value);
const cpus = std.target.getCpusForArch(arch);
const cpu_infos = cpu.ArchCpu(enum_arch).cpu_infos;
try stdout_stream.print("Available cpus for {}:\n", .{ @tagName(arch) });
try stdout_stream.print("Available cpus for {}:\n", .{ arch_enum_field.name });
var longest_len: usize = 0;
for (cpus) |cpu| {
if (cpu.name.len > longest_len) {
longest_len = cpu.name.len;
}
}
var longest_len: usize = 0;
for (cpu_infos) |cpu_info| {
if (cpu_info.name.len > longest_len) longest_len = cpu_info.name.len;
}
for (cpus) |cpu| {
try stdout_stream.print(" {}", .{ cpu.name });
var i: usize = 0;
while (i < longest_len - cpu.name.len) : (i += 1) {
try stdout_stream.write(" ");
}
for (cpu_infos) |cpu_info| {
try stdout_stream.print(" {}", .{ cpu_info.name });
var i: usize = 0;
while (i < longest_len - cpu_info.name.len) : (i += 1) {
try stdout_stream.write(" ");
}
try stdout_stream.write("\n");
try stdout_stream.write("\n");
if (show_subfeatures and cpu_info.features.len > 0) {
for (cpu_info.features) |subfeature| {
try stdout_stream.print(" {}\n", .{ subfeature.getInfo().name });
}
}
if (show_subfeatures and cpu.subfeatures.len > 0) {
for (cpu.subfeatures) |subfeature| {
try stdout_stream.print(" {}\n", .{ subfeature.name });
}
}
}
}
// use target_arch_name(ZigLLVM_ArchType) to get name from main.cpp 'target'.