zig

commit c39bb3ebc49096af45f3a69d4742e5f4d50cab62 (tree)
parent 6529658ad861bc47e9641081bb953ba54f21a1ae
Author: Andrew Kelley <andrew@ziglang.org>
Date:   Fri, 16 Aug 2019 16:52:45 -0400

target: add missing switch case

Diffstat:
M
src/target.cpp
 | 
2
++

1 file changed, 2 insertions(+), 0 deletions(-)
diff --git a/src/target.cpp b/src/target.cpp
@@ -686,6 +686,8 @@ const char *target_subarch_name(ZigLLVM_SubArchType subarch) {
             return "v8m_baseline";
         case ZigLLVM_ARMSubArch_v8m_mainline:
             return "v8m_mainline";
+        case ZigLLVM_ARMSubArch_v8_1m_mainline:
+            return "v8_1m_mainline";
         case ZigLLVM_ARMSubArch_v7:
             return "v7";
         case ZigLLVM_ARMSubArch_v7em: