Merge pull request #10066 from joachimschmidt557/stage2-aarch64-mir
stage2 AArch64: introduce MIR
This commit is contained in:
Jakub Konka
File diff suppressed because it is too large
Load Diff
419
src/arch/aarch64/Emit.zig
Normal file
419
src/arch/aarch64/Emit.zig
Normal file
@@ -0,0 +1,419 @@
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//! This file contains the functionality for lowering AArch64 MIR into
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//! machine code
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const Emit = @This();
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const std = @import("std");
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const math = std.math;
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const Mir = @import("Mir.zig");
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const bits = @import("bits.zig");
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const link = @import("../../link.zig");
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const Module = @import("../../Module.zig");
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const ErrorMsg = Module.ErrorMsg;
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const assert = std.debug.assert;
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const DW = std.dwarf;
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const leb128 = std.leb;
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const Instruction = bits.Instruction;
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const Register = bits.Register;
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const DebugInfoOutput = @import("../../codegen.zig").DebugInfoOutput;
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mir: Mir,
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bin_file: *link.File,
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debug_output: DebugInfoOutput,
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target: *const std.Target,
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err_msg: ?*ErrorMsg = null,
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src_loc: Module.SrcLoc,
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code: *std.ArrayList(u8),
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prev_di_line: u32,
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prev_di_column: u32,
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/// Relative to the beginning of `code`.
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prev_di_pc: usize,
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const InnerError = error{
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OutOfMemory,
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EmitFail,
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};
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pub fn emitMir(
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emit: *Emit,
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) !void {
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const mir_tags = emit.mir.instructions.items(.tag);
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for (mir_tags) |tag, index| {
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const inst = @intCast(u32, index);
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switch (tag) {
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.add_immediate => try emit.mirAddSubtractImmediate(inst),
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.sub_immediate => try emit.mirAddSubtractImmediate(inst),
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.b => try emit.mirBranch(inst),
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.bl => try emit.mirBranch(inst),
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.blr => try emit.mirUnconditionalBranchRegister(inst),
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.ret => try emit.mirUnconditionalBranchRegister(inst),
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.brk => try emit.mirExceptionGeneration(inst),
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.svc => try emit.mirExceptionGeneration(inst),
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.call_extern => try emit.mirCallExtern(inst),
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.dbg_line => try emit.mirDbgLine(inst),
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.dbg_prologue_end => try emit.mirDebugPrologueEnd(),
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.dbg_epilogue_begin => try emit.mirDebugEpilogueBegin(),
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.load_memory => try emit.mirLoadMemory(inst),
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.ldp => try emit.mirLoadStoreRegisterPair(inst),
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.stp => try emit.mirLoadStoreRegisterPair(inst),
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.ldr => try emit.mirLoadStoreRegister(inst),
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.ldrb => try emit.mirLoadStoreRegister(inst),
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.ldrh => try emit.mirLoadStoreRegister(inst),
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.str => try emit.mirLoadStoreRegister(inst),
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.strb => try emit.mirLoadStoreRegister(inst),
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.strh => try emit.mirLoadStoreRegister(inst),
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.mov_register => try emit.mirMoveRegister(inst),
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.mov_to_from_sp => try emit.mirMoveRegister(inst),
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.movk => try emit.mirMoveWideImmediate(inst),
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.movz => try emit.mirMoveWideImmediate(inst),
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.nop => try emit.mirNop(),
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}
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}
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}
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fn writeInstruction(emit: *Emit, instruction: Instruction) !void {
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const endian = emit.target.cpu.arch.endian();
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std.mem.writeInt(u32, try emit.code.addManyAsArray(4), instruction.toU32(), endian);
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}
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fn fail(emit: *Emit, comptime format: []const u8, args: anytype) InnerError {
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@setCold(true);
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assert(emit.err_msg == null);
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emit.err_msg = try ErrorMsg.create(emit.bin_file.allocator, emit.src_loc, format, args);
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return error.EmitFail;
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}
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fn moveImmediate(emit: *Emit, reg: Register, imm64: u64) !void {
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try emit.writeInstruction(Instruction.movz(reg, @truncate(u16, imm64), 0));
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if (imm64 > math.maxInt(u16)) {
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try emit.writeInstruction(Instruction.movk(reg, @truncate(u16, imm64 >> 16), 16));
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}
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if (imm64 > math.maxInt(u32)) {
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try emit.writeInstruction(Instruction.movk(reg, @truncate(u16, imm64 >> 32), 32));
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}
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if (imm64 > math.maxInt(u48)) {
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try emit.writeInstruction(Instruction.movk(reg, @truncate(u16, imm64 >> 48), 48));
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}
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}
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fn dbgAdvancePCAndLine(self: *Emit, line: u32, column: u32) !void {
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const delta_line = @intCast(i32, line) - @intCast(i32, self.prev_di_line);
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const delta_pc: usize = self.code.items.len - self.prev_di_pc;
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switch (self.debug_output) {
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.dwarf => |dbg_out| {
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// TODO Look into using the DWARF special opcodes to compress this data.
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// It lets you emit single-byte opcodes that add different numbers to
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// both the PC and the line number at the same time.
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try dbg_out.dbg_line.ensureUnusedCapacity(11);
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dbg_out.dbg_line.appendAssumeCapacity(DW.LNS.advance_pc);
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leb128.writeULEB128(dbg_out.dbg_line.writer(), delta_pc) catch unreachable;
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if (delta_line != 0) {
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dbg_out.dbg_line.appendAssumeCapacity(DW.LNS.advance_line);
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leb128.writeILEB128(dbg_out.dbg_line.writer(), delta_line) catch unreachable;
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}
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dbg_out.dbg_line.appendAssumeCapacity(DW.LNS.copy);
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self.prev_di_pc = self.code.items.len;
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self.prev_di_line = line;
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self.prev_di_column = column;
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self.prev_di_pc = self.code.items.len;
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},
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.plan9 => |dbg_out| {
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if (delta_pc <= 0) return; // only do this when the pc changes
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// we have already checked the target in the linker to make sure it is compatable
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const quant = @import("../../link/Plan9/aout.zig").getPCQuant(self.target.cpu.arch) catch unreachable;
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// increasing the line number
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try @import("../../link/Plan9.zig").changeLine(dbg_out.dbg_line, delta_line);
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// increasing the pc
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const d_pc_p9 = @intCast(i64, delta_pc) - quant;
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if (d_pc_p9 > 0) {
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// minus one because if its the last one, we want to leave space to change the line which is one quanta
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try dbg_out.dbg_line.append(@intCast(u8, @divExact(d_pc_p9, quant) + 128) - quant);
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if (dbg_out.pcop_change_index.*) |pci|
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dbg_out.dbg_line.items[pci] += 1;
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dbg_out.pcop_change_index.* = @intCast(u32, dbg_out.dbg_line.items.len - 1);
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} else if (d_pc_p9 == 0) {
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// we don't need to do anything, because adding the quant does it for us
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} else unreachable;
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if (dbg_out.start_line.* == null)
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dbg_out.start_line.* = self.prev_di_line;
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dbg_out.end_line.* = line;
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// only do this if the pc changed
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self.prev_di_line = line;
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self.prev_di_column = column;
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self.prev_di_pc = self.code.items.len;
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},
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.none => {},
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}
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}
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fn mirAddSubtractImmediate(emit: *Emit, inst: Mir.Inst.Index) !void {
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const tag = emit.mir.instructions.items(.tag)[inst];
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const rr_imm12_sh = emit.mir.instructions.items(.data)[inst].rr_imm12_sh;
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switch (tag) {
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.add_immediate => try emit.writeInstruction(Instruction.add(
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rr_imm12_sh.rd,
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rr_imm12_sh.rn,
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rr_imm12_sh.imm12,
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rr_imm12_sh.sh == 1,
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)),
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.sub_immediate => try emit.writeInstruction(Instruction.sub(
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rr_imm12_sh.rd,
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rr_imm12_sh.rn,
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rr_imm12_sh.imm12,
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rr_imm12_sh.sh == 1,
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)),
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else => unreachable,
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}
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}
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fn mirBranch(emit: *Emit, inst: Mir.Inst.Index) !void {
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const tag = emit.mir.instructions.items(.tag)[inst];
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const target_inst = emit.mir.instructions.items(.data)[inst].inst;
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_ = tag;
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_ = target_inst;
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switch (tag) {
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.b => return emit.fail("Implement mirBranch", .{}),
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.bl => return emit.fail("Implement mirBranch", .{}),
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else => unreachable,
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}
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}
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fn mirUnconditionalBranchRegister(emit: *Emit, inst: Mir.Inst.Index) !void {
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const tag = emit.mir.instructions.items(.tag)[inst];
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const reg = emit.mir.instructions.items(.data)[inst].reg;
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switch (tag) {
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.blr => try emit.writeInstruction(Instruction.blr(reg)),
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.ret => try emit.writeInstruction(Instruction.ret(reg)),
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else => unreachable,
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}
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}
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fn mirExceptionGeneration(emit: *Emit, inst: Mir.Inst.Index) !void {
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const tag = emit.mir.instructions.items(.tag)[inst];
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const imm16 = emit.mir.instructions.items(.data)[inst].imm16;
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switch (tag) {
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.brk => try emit.writeInstruction(Instruction.brk(imm16)),
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.svc => try emit.writeInstruction(Instruction.svc(imm16)),
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else => unreachable,
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}
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}
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fn mirDbgLine(emit: *Emit, inst: Mir.Inst.Index) !void {
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const tag = emit.mir.instructions.items(.tag)[inst];
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const dbg_line_column = emit.mir.instructions.items(.data)[inst].dbg_line_column;
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switch (tag) {
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.dbg_line => try emit.dbgAdvancePCAndLine(dbg_line_column.line, dbg_line_column.column),
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else => unreachable,
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}
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}
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fn mirDebugPrologueEnd(self: *Emit) !void {
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switch (self.debug_output) {
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.dwarf => |dbg_out| {
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try dbg_out.dbg_line.append(DW.LNS.set_prologue_end);
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try self.dbgAdvancePCAndLine(self.prev_di_line, self.prev_di_column);
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},
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.plan9 => {},
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.none => {},
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}
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}
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fn mirDebugEpilogueBegin(self: *Emit) !void {
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switch (self.debug_output) {
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.dwarf => |dbg_out| {
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try dbg_out.dbg_line.append(DW.LNS.set_epilogue_begin);
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try self.dbgAdvancePCAndLine(self.prev_di_line, self.prev_di_column);
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},
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.plan9 => {},
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.none => {},
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}
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}
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fn mirCallExtern(emit: *Emit, inst: Mir.Inst.Index) !void {
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assert(emit.mir.instructions.items(.tag)[inst] == .call_extern);
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const n_strx = emit.mir.instructions.items(.data)[inst].extern_fn;
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if (emit.bin_file.cast(link.File.MachO)) |macho_file| {
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const offset = blk: {
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const offset = @intCast(u32, emit.code.items.len);
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// bl
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try emit.writeInstruction(Instruction.bl(0));
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break :blk offset;
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};
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// Add relocation to the decl.
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try macho_file.active_decl.?.link.macho.relocs.append(emit.bin_file.allocator, .{
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.offset = offset,
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.target = .{ .global = n_strx },
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.addend = 0,
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.subtractor = null,
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.pcrel = true,
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.length = 2,
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.@"type" = @enumToInt(std.macho.reloc_type_arm64.ARM64_RELOC_BRANCH26),
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});
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} else {
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return emit.fail("Implement call_extern for linking backends != MachO", .{});
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}
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}
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fn mirLoadMemory(emit: *Emit, inst: Mir.Inst.Index) !void {
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assert(emit.mir.instructions.items(.tag)[inst] == .load_memory);
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const payload = emit.mir.instructions.items(.data)[inst].payload;
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const load_memory = emit.mir.extraData(Mir.LoadMemory, payload).data;
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const reg = @intToEnum(Register, load_memory.register);
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const addr = load_memory.addr;
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if (emit.bin_file.options.pie) {
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// PC-relative displacement to the entry in the GOT table.
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// adrp
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const offset = @intCast(u32, emit.code.items.len);
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try emit.writeInstruction(Instruction.adrp(reg, 0));
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// ldr reg, reg, offset
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try emit.writeInstruction(Instruction.ldr(reg, .{
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.register = .{
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.rn = reg,
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.offset = Instruction.LoadStoreOffset.imm(0),
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},
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}));
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if (emit.bin_file.cast(link.File.MachO)) |macho_file| {
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// TODO I think the reloc might be in the wrong place.
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const decl = macho_file.active_decl.?;
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// Page reloc for adrp instruction.
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try decl.link.macho.relocs.append(emit.bin_file.allocator, .{
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.offset = offset,
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.target = .{ .local = addr },
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.addend = 0,
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.subtractor = null,
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.pcrel = true,
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.length = 2,
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.@"type" = @enumToInt(std.macho.reloc_type_arm64.ARM64_RELOC_GOT_LOAD_PAGE21),
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});
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// Pageoff reloc for adrp instruction.
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try decl.link.macho.relocs.append(emit.bin_file.allocator, .{
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.offset = offset + 4,
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.target = .{ .local = addr },
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.addend = 0,
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.subtractor = null,
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.pcrel = false,
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.length = 2,
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.@"type" = @enumToInt(std.macho.reloc_type_arm64.ARM64_RELOC_GOT_LOAD_PAGEOFF12),
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});
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} else {
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return emit.fail("TODO implement load_memory for PIE GOT indirection on this platform", .{});
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}
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} else {
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// The value is in memory at a hard-coded address.
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// If the type is a pointer, it means the pointer address is at this memory location.
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try emit.moveImmediate(reg, addr);
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try emit.writeInstruction(Instruction.ldr(
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reg,
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.{ .register = .{ .rn = reg, .offset = Instruction.LoadStoreOffset.none } },
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));
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}
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}
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fn mirLoadStoreRegisterPair(emit: *Emit, inst: Mir.Inst.Index) !void {
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const tag = emit.mir.instructions.items(.tag)[inst];
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const load_store_register_pair = emit.mir.instructions.items(.data)[inst].load_store_register_pair;
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switch (tag) {
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.stp => try emit.writeInstruction(Instruction.stp(
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load_store_register_pair.rt,
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load_store_register_pair.rt2,
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load_store_register_pair.rn,
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load_store_register_pair.offset,
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)),
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.ldp => try emit.writeInstruction(Instruction.ldp(
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load_store_register_pair.rt,
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load_store_register_pair.rt2,
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load_store_register_pair.rn,
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load_store_register_pair.offset,
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)),
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else => unreachable,
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}
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}
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fn mirLoadStoreRegister(emit: *Emit, inst: Mir.Inst.Index) !void {
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const tag = emit.mir.instructions.items(.tag)[inst];
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const load_store_register = emit.mir.instructions.items(.data)[inst].load_store_register;
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switch (tag) {
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.ldr => try emit.writeInstruction(Instruction.ldr(
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load_store_register.rt,
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.{ .register = .{ .rn = load_store_register.rn, .offset = load_store_register.offset } },
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)),
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.ldrb => try emit.writeInstruction(Instruction.ldrb(
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load_store_register.rt,
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load_store_register.rn,
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.{ .offset = load_store_register.offset },
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)),
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.ldrh => try emit.writeInstruction(Instruction.ldrh(
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load_store_register.rt,
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load_store_register.rn,
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.{ .offset = load_store_register.offset },
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)),
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.str => try emit.writeInstruction(Instruction.str(
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load_store_register.rt,
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load_store_register.rn,
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.{ .offset = load_store_register.offset },
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)),
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.strb => try emit.writeInstruction(Instruction.strb(
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load_store_register.rt,
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load_store_register.rn,
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.{ .offset = load_store_register.offset },
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)),
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.strh => try emit.writeInstruction(Instruction.strh(
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load_store_register.rt,
|
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load_store_register.rn,
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.{ .offset = load_store_register.offset },
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)),
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else => unreachable,
|
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}
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}
|
||||
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fn mirMoveRegister(emit: *Emit, inst: Mir.Inst.Index) !void {
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const tag = emit.mir.instructions.items(.tag)[inst];
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const rr = emit.mir.instructions.items(.data)[inst].rr;
|
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switch (tag) {
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.mov_register => try emit.writeInstruction(Instruction.orr(rr.rd, .xzr, rr.rn, Instruction.Shift.none)),
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.mov_to_from_sp => try emit.writeInstruction(Instruction.add(rr.rd, rr.rn, 0, false)),
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else => unreachable,
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}
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}
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fn mirMoveWideImmediate(emit: *Emit, inst: Mir.Inst.Index) !void {
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const tag = emit.mir.instructions.items(.tag)[inst];
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const r_imm16_sh = emit.mir.instructions.items(.data)[inst].r_imm16_sh;
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switch (tag) {
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.movz => try emit.writeInstruction(Instruction.movz(r_imm16_sh.rd, r_imm16_sh.imm16, @as(u6, r_imm16_sh.hw) << 4)),
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.movk => try emit.writeInstruction(Instruction.movk(r_imm16_sh.rd, r_imm16_sh.imm16, @as(u6, r_imm16_sh.hw) << 4)),
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else => unreachable,
|
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}
|
||||
}
|
||||
|
||||
fn mirNop(emit: *Emit) !void {
|
||||
try emit.writeInstruction(Instruction.nop());
|
||||
}
|
||||
208
src/arch/aarch64/Mir.zig
Normal file
208
src/arch/aarch64/Mir.zig
Normal file
@@ -0,0 +1,208 @@
|
||||
//! Machine Intermediate Representation.
|
||||
//! This data is produced by AArch64 Codegen or AArch64 assembly parsing
|
||||
//! These instructions have a 1:1 correspondence with machine code instructions
|
||||
//! for the target. MIR can be lowered to source-annotated textual assembly code
|
||||
//! instructions, or it can be lowered to machine code.
|
||||
//! The main purpose of MIR is to postpone the assignment of offsets until Isel,
|
||||
//! so that, for example, the smaller encodings of jump instructions can be used.
|
||||
|
||||
const Mir = @This();
|
||||
const std = @import("std");
|
||||
const builtin = @import("builtin");
|
||||
const assert = std.debug.assert;
|
||||
|
||||
const bits = @import("bits.zig");
|
||||
const Register = bits.Register;
|
||||
|
||||
instructions: std.MultiArrayList(Inst).Slice,
|
||||
/// The meaning of this data is determined by `Inst.Tag` value.
|
||||
extra: []const u32,
|
||||
|
||||
pub const Inst = struct {
|
||||
tag: Tag,
|
||||
/// The meaning of this depends on `tag`.
|
||||
data: Data,
|
||||
|
||||
pub const Tag = enum(u16) {
|
||||
/// Add (immediate)
|
||||
add_immediate,
|
||||
/// Branch
|
||||
b,
|
||||
/// Branch with Link
|
||||
bl,
|
||||
/// Branch with Link to Register
|
||||
blr,
|
||||
/// Breakpoint
|
||||
brk,
|
||||
/// Pseudo-instruction: Call extern
|
||||
call_extern,
|
||||
/// Pseudo-instruction: End of prologue
|
||||
dbg_prologue_end,
|
||||
/// Pseudo-instruction: Beginning of epilogue
|
||||
dbg_epilogue_begin,
|
||||
/// Pseudo-instruction: Update debug line
|
||||
dbg_line,
|
||||
/// Psuedo-instruction: Load memory
|
||||
///
|
||||
/// Payload is `LoadMemory`
|
||||
load_memory,
|
||||
/// Load Pair of Registers
|
||||
ldp,
|
||||
/// Load Register
|
||||
// TODO: split into ldr_immediate and ldr_register
|
||||
ldr,
|
||||
/// Load Register Byte
|
||||
// TODO: split into ldrb_immediate and ldrb_register
|
||||
ldrb,
|
||||
/// Load Register Halfword
|
||||
// TODO: split into ldrh_immediate and ldrh_register
|
||||
ldrh,
|
||||
/// Move (to/from SP)
|
||||
mov_to_from_sp,
|
||||
/// Move (register)
|
||||
mov_register,
|
||||
/// Move wide with keep
|
||||
movk,
|
||||
/// Move wide with zero
|
||||
movz,
|
||||
/// No Operation
|
||||
nop,
|
||||
/// Return from subroutine
|
||||
ret,
|
||||
/// Store Pair of Registers
|
||||
stp,
|
||||
/// Store Register
|
||||
// TODO: split into str_immediate and str_register
|
||||
str,
|
||||
/// Store Register Byte
|
||||
// TODO: split into strb_immediate and strb_register
|
||||
strb,
|
||||
/// Store Register Halfword
|
||||
// TODO: split into strh_immediate and strh_register
|
||||
strh,
|
||||
/// Subtract (immediate)
|
||||
sub_immediate,
|
||||
/// Supervisor Call
|
||||
svc,
|
||||
};
|
||||
|
||||
/// The position of an MIR instruction within the `Mir` instructions array.
|
||||
pub const Index = u32;
|
||||
|
||||
/// All instructions have a 4-byte payload, which is contained within
|
||||
/// this union. `Tag` determines which union field is active, as well as
|
||||
/// how to interpret the data within.
|
||||
pub const Data = union {
|
||||
/// No additional data
|
||||
///
|
||||
/// Used by e.g. nop
|
||||
nop: void,
|
||||
/// Another instruction.
|
||||
///
|
||||
/// Used by e.g. b
|
||||
inst: Index,
|
||||
/// An extern function
|
||||
///
|
||||
/// Used by e.g. call_extern
|
||||
extern_fn: u32,
|
||||
/// A 16-bit immediate value.
|
||||
///
|
||||
/// Used by e.g. svc
|
||||
imm16: u16,
|
||||
/// Index into `extra`. Meaning of what can be found there is context-dependent.
|
||||
///
|
||||
/// Used by e.g. load_memory
|
||||
payload: u32,
|
||||
/// A register
|
||||
///
|
||||
/// Used by e.g. blr
|
||||
reg: Register,
|
||||
/// A register, an unsigned 16-bit immediate, and an optional shift
|
||||
///
|
||||
/// Used by e.g. movz
|
||||
r_imm16_sh: struct {
|
||||
rd: Register,
|
||||
imm16: u16,
|
||||
hw: u2 = 0,
|
||||
},
|
||||
/// Two registers
|
||||
///
|
||||
/// Used by e.g. mov_register
|
||||
rr: struct {
|
||||
rd: Register,
|
||||
rn: Register,
|
||||
},
|
||||
/// Two registers, an unsigned 12-bit immediate, and an optional shift
|
||||
///
|
||||
/// Used by e.g. sub_immediate
|
||||
rr_imm12_sh: struct {
|
||||
rd: Register,
|
||||
rn: Register,
|
||||
imm12: u12,
|
||||
sh: u1 = 0,
|
||||
},
|
||||
/// Three registers and a LoadStoreOffset
|
||||
///
|
||||
/// Used by e.g. str_register
|
||||
load_store_register: struct {
|
||||
rt: Register,
|
||||
rn: Register,
|
||||
offset: bits.Instruction.LoadStoreOffset,
|
||||
},
|
||||
/// Three registers and a LoadStorePairOffset
|
||||
///
|
||||
/// Used by e.g. stp
|
||||
load_store_register_pair: struct {
|
||||
rt: Register,
|
||||
rt2: Register,
|
||||
rn: Register,
|
||||
offset: bits.Instruction.LoadStorePairOffset,
|
||||
},
|
||||
/// Debug info: line and column
|
||||
///
|
||||
/// Used by e.g. dbg_line
|
||||
dbg_line_column: struct {
|
||||
line: u32,
|
||||
column: u32,
|
||||
},
|
||||
};
|
||||
|
||||
// Make sure we don't accidentally make instructions bigger than expected.
|
||||
// Note that in Debug builds, Zig is allowed to insert a secret field for safety checks.
|
||||
// comptime {
|
||||
// if (builtin.mode != .Debug) {
|
||||
// assert(@sizeOf(Inst) == 8);
|
||||
// }
|
||||
// }
|
||||
};
|
||||
|
||||
pub fn deinit(mir: *Mir, gpa: *std.mem.Allocator) void {
|
||||
mir.instructions.deinit(gpa);
|
||||
gpa.free(mir.extra);
|
||||
mir.* = undefined;
|
||||
}
|
||||
|
||||
/// Returns the requested data, as well as the new index which is at the start of the
|
||||
/// trailers for the object.
|
||||
pub fn extraData(mir: Mir, comptime T: type, index: usize) struct { data: T, end: usize } {
|
||||
const fields = std.meta.fields(T);
|
||||
var i: usize = index;
|
||||
var result: T = undefined;
|
||||
inline for (fields) |field| {
|
||||
@field(result, field.name) = switch (field.field_type) {
|
||||
u32 => mir.extra[i],
|
||||
i32 => @bitCast(i32, mir.extra[i]),
|
||||
else => @compileError("bad field type"),
|
||||
};
|
||||
i += 1;
|
||||
}
|
||||
return .{
|
||||
.data = result,
|
||||
.end = i,
|
||||
};
|
||||
}
|
||||
|
||||
pub const LoadMemory = struct {
|
||||
register: u32,
|
||||
addr: u32,
|
||||
};
|
||||
@@ -88,9 +88,10 @@ pub fn generateFunction(
|
||||
.wasm64 => unreachable, // has its own code path
|
||||
.arm => return Function(.arm).generate(bin_file, src_loc, func, air, liveness, code, debug_output),
|
||||
.armeb => return Function(.armeb).generate(bin_file, src_loc, func, air, liveness, code, debug_output),
|
||||
.aarch64 => return @import("arch/aarch64/CodeGen.zig").generate(.aarch64, bin_file, src_loc, func, air, liveness, code, debug_output),
|
||||
.aarch64_be => return @import("arch/aarch64/CodeGen.zig").generate(.aarch64_be, bin_file, src_loc, func, air, liveness, code, debug_output),
|
||||
.aarch64_32 => return @import("arch/aarch64/CodeGen.zig").generate(.aarch64_32, bin_file, src_loc, func, air, liveness, code, debug_output),
|
||||
.aarch64,
|
||||
.aarch64_be,
|
||||
.aarch64_32,
|
||||
=> return @import("arch/aarch64/CodeGen.zig").generate(bin_file, src_loc, func, air, liveness, code, debug_output),
|
||||
//.arc => return Function(.arc).generate(bin_file, src_loc, func, air, liveness, code, debug_output),
|
||||
//.avr => return Function(.avr).generate(bin_file, src_loc, func, air, liveness, code, debug_output),
|
||||
//.bpfel => return Function(.bpfel).generate(bin_file, src_loc, func, air, liveness, code, debug_output),
|
||||
|
||||
Reference in New Issue
Block a user