zig

commit c641fb8f05cfbca7484a09496f33bc9c2d95941e (tree)
parent 5b03d55c5ecf697086db7c454e0f3982fec42408
Author: William Sengir <william@sengir.com>
Date:   Sat, 26 Mar 2022 15:40:31 -0700

stage2: fix {add,sub,mul}_with_overflow vectorization in LLVM backend

Diffstat:
M
src/codegen/llvm.zig
 | 
3
++-

1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/codegen/llvm.zig b/src/codegen/llvm.zig
@@ -5604,8 +5604,9 @@ pub const FuncGen = struct {
         const rhs = try self.resolveInst(extra.rhs);
 
         const lhs_ty = self.air.typeOf(extra.lhs);
+        const scalar_ty = lhs_ty.scalarType();
 
-        const intrinsic_name = if (lhs_ty.isSignedInt()) signed_intrinsic else unsigned_intrinsic;
+        const intrinsic_name = if (scalar_ty.isSignedInt()) signed_intrinsic else unsigned_intrinsic;
 
         const llvm_lhs_ty = try self.dg.llvmType(lhs_ty);