zig

commit c824ce954ee81d438613ea7cf1e9a8111f730732 (tree)
parent 2037dba90f5815f6fc3137c2485e908700c009e5
Author: Nathan Bourgeois <iridescentrosesfall@gmail.com>
Date:   Sat, 21 Mar 2026 19:39:04 -0400

misc: Add allegrex CPU & features, run tool, update semver

Diffstat:
M
lib/std/Target.zig
 | 
6
++++--
M
lib/std/Target/mips.zig
 | 
15
+++++++++++++++
M
tools/update_cpu_features.zig
 | 
14
++++++++++++++

3 files changed, 33 insertions(+), 2 deletions(-)
diff --git a/lib/std/Target.zig b/lib/std/Target.zig
@@ -616,7 +616,9 @@ pub const Os = struct {
 
                 .psp => .{
                     .semver = .{
-                        .min = .{ .major = 1, .minor = 0, .patch = 0 },
+                        // https://www.psdevwiki.com/psp/Official_Firmware_(OFW)#1.XX_Kernel
+                        // It appears that the kernel started with semver for 1.XX before later changing to MAJ.MINPATCH in later releases (e.g. 3.60, 6.61)
+                        .min = .{ .major = 1, .minor = 0, .patch = 3 },
                         .max = .{ .major = 6, .minor = 61, .patch = 0 },
                     },
                 },
@@ -2034,7 +2036,7 @@ pub const Cpu = struct {
                 .loongarch64 => &loongarch.cpu.la64v1_0,
                 .m68k => &m68k.cpu.M68000,
                 .mips, .mipsel => switch (os.tag) {
-                    .psp => &mips.cpu.mips2, // mips2 with some custom instructions, no trap instructions
+                    .psp => &mips.cpu.allegrex,
                     else => &mips.cpu.mips32r2,
                 },
                 .mips64, .mips64el => &mips.cpu.mips64r2,
diff --git a/lib/std/Target/mips.zig b/lib/std/Target/mips.zig
@@ -49,6 +49,7 @@ pub const Feature = enum {
     noabicalls,
     nomadd4,
     nooddspreg,
+    notraps,
     p5600,
     ptr64,
     single_float,
@@ -353,6 +354,11 @@ pub const all_features = blk: {
         .description = "Disable odd numbered single-precision registers",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@intFromEnum(Feature.notraps)] = .{
+        .llvm_name = null,
+        .description = "Disable trap instructions",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@intFromEnum(Feature.p5600)] = .{
         .llvm_name = "p5600",
         .description = "The P5600 Processor",
@@ -419,6 +425,15 @@ pub const all_features = blk: {
 };
 
 pub const cpu = struct {
+    pub const allegrex: CpuModel = .{
+        .name = "allegrex",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .mips2,
+            .notraps,
+            .single_float,
+        }),
+    };
     pub const generic: CpuModel = .{
         .name = "generic",
         .llvm_name = "generic",
diff --git a/tools/update_cpu_features.zig b/tools/update_cpu_features.zig
@@ -1299,6 +1299,20 @@ const targets = [_]ArchTarget{
             .name = "Mips",
             .td_name = "Mips",
         },
+        .extra_features = &.{
+            .{
+                .zig_name = "notraps",
+                .desc = "Disable trap instructions",
+                .deps = &.{},
+            },
+        },
+        .extra_cpus = &.{
+            .{
+                .llvm_name = null,
+                .zig_name = "allegrex",
+                .features = &.{ "mips2", "single_float", "notraps" },
+            },
+        },
     },
     .{
         .zig_name = "nvptx",