zig

commit cbef1f5a013c664979e68d3ea8fa3ba378e3f0f6 (tree)
parent 664c1d0198c1d5027167461cc0013faf5fc53347
Author: Matthew Lugg <mlugg@mlugg.co.uk>
Date:   Tue, 23 Jun 2026 09:59:02 +0100

c_abi: disable some tests on ARM

This is an existing bug which has started causing a miscompilation in
this branch due to changes to our emitted LLVM IR.

Tracked by https://codeberg.org/ziglang/zig/issues/35899.

Diffstat:
M
test/c_abi/main.zig
 | 
2
++

1 file changed, 2 insertions(+), 0 deletions(-)
diff --git a/test/c_abi/main.zig b/test/c_abi/main.zig
@@ -14501,6 +14501,7 @@ test "@Vector(4, f64)" {
     if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;
     if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
     if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
+    if (builtin.cpu.arch.isArm()) return error.SkipZigTest; // https://codeberg.org/ziglang/zig/issues/35899
 
     const v = c_ret_vector_4_f64();
     try expect(v[0] == 33);
@@ -14570,6 +14571,7 @@ test "@Vector(8, f64)" {
     if (builtin.cpu.arch.isMIPS32()) return error.SkipZigTest;
     if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
     if (builtin.cpu.arch == .s390x) return error.SkipZigTest;
+    if (builtin.cpu.arch.isArm()) return error.SkipZigTest; // https://codeberg.org/ziglang/zig/issues/35899
 
     const v = c_ret_vector_8_f64();
     try expect(v[0] == 81);