zig

commit ceebcb2b4dec91d3c57e9c44a10f51a5a4e14899 (tree)
parent 2ad263658872a7b8b7bf3275c35d0e4c4faebccd
Author: joachimschmidt557 <joachim.schmidt557@outlook.com>
Date:   Sat, 28 Nov 2020 19:02:07 +0100

stage2 ARM: add test case for addition

Diffstat:
M
test/stage2/arm.zig
 | 
36
++++++++++++++++++++++++++++++++++++

1 file changed, 36 insertions(+), 0 deletions(-)
diff --git a/test/stage2/arm.zig b/test/stage2/arm.zig
@@ -113,4 +113,40 @@ pub fn addCases(ctx: *TestContext) !void {
             "",
         );
     }
+
+    {
+        var case = ctx.exe("addition", linux_arm);
+        // Add two numbers
+        case.addCompareOutput(
+            \\export fn _start() noreturn {
+            \\    print(2, 4);
+            \\    print(1, 7);
+            \\    exit();
+            \\}
+            \\
+            \\fn print(a: u32, b: u32) void {
+            \\    asm volatile ("svc #0"
+            \\        :
+            \\        : [number] "{r7}" (4),
+            \\          [arg3] "{r2}" (a + b),
+            \\          [arg1] "{r0}" (1),
+            \\          [arg2] "{r1}" (@ptrToInt("123456789"))
+            \\        : "memory"
+            \\    );
+            \\    return;
+            \\}
+            \\
+            \\fn exit() noreturn {
+            \\    asm volatile ("svc #0"
+            \\        :
+            \\        : [number] "{r7}" (1),
+            \\          [arg1] "{r0}" (0)
+            \\        : "memory"
+            \\    );
+            \\    unreachable;
+            \\}
+        ,
+            "12345612345678",
+        );
+    }
 }