zig

commit d3edf298d18ff89bb0e0a3bfcee84a9fb63b1c6b (tree)
parent 1b7ec44924ede3816438f9de4b4b5bc3b7705711
Author: Jakub Konka <kubkon@jakubkonka.com>
Date:   Wed, 16 Feb 2022 15:24:04 +0100

x64: fix signed truncate

Diffstat:
M
src/arch/x86_64/CodeGen.zig
 | 
3
+--

1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/arch/x86_64/CodeGen.zig b/src/arch/x86_64/CodeGen.zig
@@ -966,7 +966,7 @@ fn airTrunc(self: *Self, inst: Air.Inst.Index) !void {
     const reg: Register = blk: {
         if (operand.isRegister()) {
             if (self.reuseOperand(inst, ty_op.operand, 0, operand)) {
-                break :blk operand.register;
+                break :blk operand.register.to64();
             }
         }
         const mcv = try self.copyToNewRegister(inst, src_ty, operand);
@@ -2300,7 +2300,6 @@ fn genBinMathOp(self: *Self, inst: Air.Inst.Index, op_lhs: Air.Inst.Ref, op_rhs:
     const mcvs = try self.mcvsForBinMathOp(inst, op_lhs, op_rhs);
     const dst_mcv = mcvs.dst;
     const src_mcv = mcvs.src;
-    log.warn("dst_mcv = {}, src_mcv = {}", .{ dst_mcv, src_mcv });
     const tag = self.air.instructions.items(.tag)[inst];
     switch (tag) {
         .add, .addwrap => try self.genBinMathOpMir(.add, dst_ty, dst_mcv, src_mcv),