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std.Target: Remove the tce/tcele arch tags.

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There is no obvious reason why this would be relevant for Zig to target. I
rather question the value of LLVM even having target triple code for this, too.

See: https://blog.llvm.org/2010/06/tce-project-co-design-of-application.html
See: https://github.com/cpc/llvmtce
This commit is contained in:
Alex Rønne Petersen
2024-07-21 14:17:51 +02:00
parent 21cc5a2044
commit db8bc4770c
6 changed files with 1 additions and 51 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
lib/compiler/aro/aro/target.zig vendored
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@@ -17,8 +17,6 @@ pub fn intMaxType(target: std.Target) Type {
.riscv64,
.powerpc64,
.powerpc64le,
.tce,
.tcele,
.ve,
=> return .{ .specifier = .long },
@@ -54,8 +52,6 @@ pub fn intPtrType(target: std.Target) Type {
.riscv32,
.xcore,
.hexagon,
.tce,
.tcele,
.m68k,
.spir,
.spirv32,
@@ -153,7 +149,7 @@ pub fn isTlsSupported(target: std.Target) bool {
return supported;
}
return switch (target.cpu.arch) {
.tce, .tcele, .bpfel, .bpfeb, .msp430, .nvptx, .nvptx64, .x86, .arm, .armeb, .thumb, .thumbeb => false,
.bpfel, .bpfeb, .msp430, .nvptx, .nvptx64, .x86, .arm, .armeb, .thumb, .thumbeb => false,
else => true,
};
}
@@ -473,8 +469,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
.riscv32,
.sparc,
.sparcel,
.tce,
.tcele,
.thumb,
.thumbeb,
.x86,
@@ -523,8 +517,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
.msp430,
.sparcel,
.spu_2,
.tce,
.tcele,
.xcore,
.xtensa,
=> return null,
@@ -611,8 +603,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
.sparc64 => "sparc64",
.sparcel => "sparcel",
.s390x => "s390x",
.tce => "tce",
.tcele => "tcele",
.thumb => "thumb",
.thumbeb => "thumbeb",
.x86 => "i386",

28
lib/std/Target.zig
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@@ -1001,8 +1001,6 @@ pub const Cpu = struct {
sparc64,
sparcel,
s390x,
tce,
tcele,
thumb,
thumbeb,
x86,
@@ -1143,8 +1141,6 @@ pub const Cpu = struct {
.riscv32 => .RISCV,
.sparc => .SPARC,
.sparcel => .SPARC,
.tce => .NONE,
.tcele => .NONE,
.thumb => .ARM,
.thumbeb => .ARM,
.x86 => .@"386",
@@ -1199,8 +1195,6 @@ pub const Cpu = struct {
.riscv32 => .RISCV32,
.sparc => .Unknown,
.sparcel => .Unknown,
.tce => .Unknown,
.tcele => .Unknown,
.thumb => .Thumb,
.thumbeb => .Thumb,
.x86 => .I386,
@@ -1257,7 +1251,6 @@ pub const Cpu = struct {
.nvptx,
.nvptx64,
.sparcel,
.tcele,
.powerpcle,
.powerpc64le,
.riscv32,
@@ -1293,7 +1286,6 @@ pub const Cpu = struct {
.thumbeb,
.sparc,
.sparc64,
.tce,
.lanai,
.s390x,
=> .big,
@@ -1749,8 +1741,6 @@ pub const DynamicLinker = struct {
.m68k,
.msp430,
.amdgcn,
.tce,
.tcele,
.xcore,
.spir,
.spir64,
@@ -1846,8 +1836,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
.powerpcle,
.riscv32,
.sparcel,
.tce,
.tcele,
.thumb,
.thumbeb,
.x86,
@@ -2022,12 +2010,6 @@ pub fn c_type_bit_size(target: Target, c_type: CType) u16 {
.long, .ulong, .float, .double, .longdouble => return 32,
.longlong, .ulonglong => return 64,
},
.tce, .tcele => switch (c_type) {
.char => return 8,
.short, .ushort => return 16,
.int, .uint, .long, .ulong, .longlong, .ulonglong => return 32,
.float, .double, .longdouble => return 32,
},
.mips64, .mips64el => switch (c_type) {
.char => return 8,
.short, .ushort => return 16,
@@ -2117,12 +2099,6 @@ pub fn c_type_bit_size(target: Target, c_type: CType) u16 {
.long, .ulong, .float, .double, .longdouble => return 32,
.longlong, .ulonglong => return 64,
},
.tce, .tcele => switch (c_type) {
.char => return 8,
.short, .ushort => return 16,
.int, .uint, .long, .ulong, .longlong, .ulonglong => return 32,
.float, .double, .longdouble => return 32,
},
.mips64, .mips64el => switch (c_type) {
.char => return 8,
.short, .ushort => return 16,
@@ -2370,8 +2346,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {
.xcore,
.dxil,
.loongarch32,
.tce,
.tcele,
.spir,
.spirv32,
.kalimba,
@@ -2481,8 +2455,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {
.xcore,
.dxil,
.loongarch32,
.tce,
.tcele,
.spir,
.spirv32,
.kalimba,

2
src/Type.zig
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@@ -1648,8 +1648,6 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 {
.csky,
.arc,
.m68k,
.tce,
.tcele,
.spir,
.kalimba,
.spirv,

2
src/Zcu.zig
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@@ -3249,8 +3249,6 @@ pub fn atomicPtrAlignment(
.riscv32,
.sparc,
.sparcel,
.tce,
.tcele,
.thumb,
.thumbeb,
.x86,

6
src/codegen/llvm.zig
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@@ -72,8 +72,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
.sparc64 => "sparc64",
.sparcel => "sparcel",
.s390x => "s390x",
.tce => "tce",
.tcele => "tcele",
.thumb => "thumb",
.thumbeb => "thumbeb",
.x86 => "i386",
@@ -288,8 +286,6 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType {
.sparc64 => .sparcv9, // In LLVM, sparc64 == sparcv9.
.sparcel => .sparcel,
.s390x => .systemz,
.tce => .tce,
.tcele => .tcele,
.thumb => .thumb,
.thumbeb => .thumbeb,
.x86 => .x86,
@@ -12076,8 +12072,6 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
},
// LLVM backends that have no initialization functions.
.tce,
.tcele,
.spir,
.spir64,
.spirv,

2
src/target.zig
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@@ -142,8 +142,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {
.sparc64,
.sparcel,
.s390x,
.tce,
.tcele,
.thumb,
.thumbeb,
.x86,