zig

commit db9058e41a7b11fcf0c1742fc7eac8a67fab3bcf (tree)
parent 6e6ae8886e6885a648918cdb006f899b40b378aa
Author: Cody Tapscott <topolarity@tapscott.me>
Date:   Sat,  8 Oct 2022 11:32:32 -0700

Disable llvm.prefetch for PowerPC

This instruction is not supported on this backend, so should
just be a noop.

Diffstat:
M
src/codegen/llvm.zig
 | 
8
+++++++-
M
src/stage1/codegen.cpp
 | 
4
++++

2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/src/codegen/llvm.zig b/src/codegen/llvm.zig
@@ -9168,7 +9168,13 @@ pub const FuncGen = struct {
         const target = self.dg.module.getTarget();
         switch (prefetch.cache) {
             .instruction => switch (target.cpu.arch) {
-                .x86_64, .i386 => return null,
+                .x86_64,
+                .i386,
+                .powerpc,
+                .powerpcle,
+                .powerpc64,
+                .powerpc64le,
+                => return null,
                 .arm, .armeb, .thumb, .thumbeb => {
                     switch (prefetch.rw) {
                         .write => return null,
diff --git a/src/stage1/codegen.cpp b/src/stage1/codegen.cpp
@@ -6742,6 +6742,10 @@ static LLVMValueRef ir_render_prefetch(CodeGen *g, Stage1Air *executable, Stage1
         switch (g->zig_target->arch) {
             case ZigLLVM_x86:
             case ZigLLVM_x86_64:
+            case ZigLLVM_ppc:
+            case ZigLLVM_ppcle:
+            case ZigLLVM_ppc64:
+            case ZigLLVM_ppc64le:
                 return nullptr;
             default:
                 break;