std: Add many more vendors and cpus to the ARM detection list
Hand-picked from GCC and LLVM lists.
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LemonBoy
@@ -163,61 +163,113 @@ const ArmCpuinfoImpl = struct {
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const A32 = Target.arm.cpu;
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const A64 = Target.aarch64.cpu;
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// implementer = 0x41
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const ARM = .{
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.{ 0x926, &A32.arm926ej_s, null },
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.{ 0xb02, &A32.mpcore, null },
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.{ 0xb36, &A32.arm1136j_s, null },
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.{ 0xb56, &A32.arm1156t2_s, null },
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.{ 0xb76, &A32.arm1176jz_s, null },
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.{ 0xc05, &A32.cortex_a5, null },
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.{ 0xc07, &A32.cortex_a7, null },
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.{ 0xc08, &A32.cortex_a8, null },
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.{ 0xc09, &A32.cortex_a9, null },
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.{ 0xc0d, &A32.cortex_a17, null },
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.{ 0xc0f, &A32.cortex_a15, null },
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.{ 0xc0e, &A32.cortex_a17, null },
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.{ 0xc14, &A32.cortex_r4, null },
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.{ 0xc15, &A32.cortex_r5, null },
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.{ 0xc17, &A32.cortex_r7, null },
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.{ 0xc18, &A32.cortex_r8, null },
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.{ 0xc20, &A32.cortex_m0, null },
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.{ 0xc21, &A32.cortex_m1, null },
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.{ 0xc23, &A32.cortex_m3, null },
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.{ 0xc24, &A32.cortex_m4, null },
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.{ 0xc27, &A32.cortex_m7, null },
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.{ 0xc60, &A32.cortex_m0plus, null },
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.{ 0xd01, &A32.cortex_a32, null },
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.{ 0xd03, &A32.cortex_a53, &A64.cortex_a53 },
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.{ 0xd04, &A32.cortex_a35, &A64.cortex_a35 },
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.{ 0xd05, &A32.cortex_a55, &A64.cortex_a55 },
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.{ 0xd07, &A32.cortex_a57, &A64.cortex_a57 },
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.{ 0xd08, &A32.cortex_a72, &A64.cortex_a72 },
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.{ 0xd09, &A32.cortex_a73, &A64.cortex_a73 },
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.{ 0xd0a, &A32.cortex_a75, &A64.cortex_a75 },
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.{ 0xd0b, &A32.cortex_a76, &A64.cortex_a76 },
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.{ 0xd0c, &A32.neoverse_n1, null },
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.{ 0xd0d, &A32.cortex_a77, &A64.cortex_a77 },
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.{ 0xd13, &A32.cortex_r52, null },
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.{ 0xd20, &A32.cortex_m23, null },
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.{ 0xd21, &A32.cortex_m33, null },
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.{ 0xd41, &A32.cortex_a78, &A64.cortex_a78 },
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.{ 0xd4b, &A32.cortex_a78c, &A64.cortex_a78c },
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.{ 0xd44, &A32.cortex_x1, &A64.cortex_x1 },
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.{ 0xd02, null, &A64.cortex_a34 },
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.{ 0xd06, null, &A64.cortex_a65 },
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.{ 0xd43, null, &A64.cortex_a65ae },
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const E = struct {
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part: u16,
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variant: ?u8 = null, // null if matches any variant
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m32: ?*const Target.Cpu.Model = null,
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m64: ?*const Target.Cpu.Model = null,
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};
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fn isKnown(implementer: u8, part: u16, is_64bit: bool) ?*const Target.Cpu.Model {
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const models = switch (implementer) {
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0x41 => ARM,
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// implementer = 0x41
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const ARM = [_]E{
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E{ .part = 0x926, .m32 = &A32.arm926ej_s, .m64 = null },
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E{ .part = 0xb02, .m32 = &A32.mpcore, .m64 = null },
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E{ .part = 0xb36, .m32 = &A32.arm1136j_s, .m64 = null },
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E{ .part = 0xb56, .m32 = &A32.arm1156t2_s, .m64 = null },
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E{ .part = 0xb76, .m32 = &A32.arm1176jz_s, .m64 = null },
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E{ .part = 0xc05, .m32 = &A32.cortex_a5, .m64 = null },
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E{ .part = 0xc07, .m32 = &A32.cortex_a7, .m64 = null },
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E{ .part = 0xc08, .m32 = &A32.cortex_a8, .m64 = null },
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E{ .part = 0xc09, .m32 = &A32.cortex_a9, .m64 = null },
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E{ .part = 0xc0d, .m32 = &A32.cortex_a17, .m64 = null },
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E{ .part = 0xc0f, .m32 = &A32.cortex_a15, .m64 = null },
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E{ .part = 0xc0e, .m32 = &A32.cortex_a17, .m64 = null },
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E{ .part = 0xc14, .m32 = &A32.cortex_r4, .m64 = null },
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E{ .part = 0xc15, .m32 = &A32.cortex_r5, .m64 = null },
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E{ .part = 0xc17, .m32 = &A32.cortex_r7, .m64 = null },
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E{ .part = 0xc18, .m32 = &A32.cortex_r8, .m64 = null },
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E{ .part = 0xc20, .m32 = &A32.cortex_m0, .m64 = null },
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E{ .part = 0xc21, .m32 = &A32.cortex_m1, .m64 = null },
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E{ .part = 0xc23, .m32 = &A32.cortex_m3, .m64 = null },
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E{ .part = 0xc24, .m32 = &A32.cortex_m4, .m64 = null },
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E{ .part = 0xc27, .m32 = &A32.cortex_m7, .m64 = null },
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E{ .part = 0xc60, .m32 = &A32.cortex_m0plus, .m64 = null },
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E{ .part = 0xd01, .m32 = &A32.cortex_a32, .m64 = null },
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E{ .part = 0xd03, .m32 = &A32.cortex_a53, .m64 = &A64.cortex_a53 },
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E{ .part = 0xd04, .m32 = &A32.cortex_a35, .m64 = &A64.cortex_a35 },
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E{ .part = 0xd05, .m32 = &A32.cortex_a55, .m64 = &A64.cortex_a55 },
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E{ .part = 0xd07, .m32 = &A32.cortex_a57, .m64 = &A64.cortex_a57 },
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E{ .part = 0xd08, .m32 = &A32.cortex_a72, .m64 = &A64.cortex_a72 },
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E{ .part = 0xd09, .m32 = &A32.cortex_a73, .m64 = &A64.cortex_a73 },
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E{ .part = 0xd0a, .m32 = &A32.cortex_a75, .m64 = &A64.cortex_a75 },
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E{ .part = 0xd0b, .m32 = &A32.cortex_a76, .m64 = &A64.cortex_a76 },
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E{ .part = 0xd0c, .m32 = &A32.neoverse_n1, .m64 = null },
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E{ .part = 0xd0d, .m32 = &A32.cortex_a77, .m64 = &A64.cortex_a77 },
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E{ .part = 0xd13, .m32 = &A32.cortex_r52, .m64 = null },
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E{ .part = 0xd20, .m32 = &A32.cortex_m23, .m64 = null },
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E{ .part = 0xd21, .m32 = &A32.cortex_m33, .m64 = null },
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E{ .part = 0xd41, .m32 = &A32.cortex_a78, .m64 = &A64.cortex_a78 },
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E{ .part = 0xd4b, .m32 = &A32.cortex_a78c, .m64 = &A64.cortex_a78c },
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E{ .part = 0xd44, .m32 = &A32.cortex_x1, .m64 = &A64.cortex_x1 },
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E{ .part = 0xd02, .m64 = &A64.cortex_a34 },
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E{ .part = 0xd06, .m64 = &A64.cortex_a65 },
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E{ .part = 0xd43, .m64 = &A64.cortex_a65ae },
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};
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// implementer = 0x42
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const Broadcom = [_]E{
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E{ .part = 0x516, .m64 = &A64.thunderx2t99 },
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};
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// implementer = 0x43
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const Cavium = [_]E{
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E{ .part = 0x0a0, .m64 = &A64.thunderx },
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E{ .part = 0x0a2, .m64 = &A64.thunderxt81 },
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E{ .part = 0x0a3, .m64 = &A64.thunderxt83 },
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E{ .part = 0x0a1, .m64 = &A64.thunderxt88 },
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E{ .part = 0x0af, .m64 = &A64.thunderx2t99 },
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};
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// implementer = 0x46
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const Fujitsu = [_]E{
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E{ .part = 0x001, .m64 = &A64.a64fx },
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};
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// implementer = 0x48
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const HiSilicon = [_]E{
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E{ .part = 0xd01, .m64 = &A64.tsv110 },
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};
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// implementer = 0x4e
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const Nvidia = [_]E{
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E{ .part = 0x004, .m64 = &A64.carmel },
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};
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// implementer = 0x51
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const Qualcomm = [_]E{
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E{ .part = 0x06f, .m32 = &A32.krait },
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E{ .part = 0x201, .m64 = &A64.kryo, .m32 = &A64.kryo },
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E{ .part = 0x205, .m64 = &A64.kryo, .m32 = &A64.kryo },
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E{ .part = 0x211, .m64 = &A64.kryo, .m32 = &A64.kryo },
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E{ .part = 0x800, .m64 = &A64.cortex_a73, .m32 = &A64.cortex_a73 },
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E{ .part = 0x801, .m64 = &A64.cortex_a73, .m32 = &A64.cortex_a73 },
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E{ .part = 0x802, .m64 = &A64.cortex_a75, .m32 = &A64.cortex_a75 },
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E{ .part = 0x803, .m64 = &A64.cortex_a75, .m32 = &A64.cortex_a75 },
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E{ .part = 0x804, .m64 = &A64.cortex_a76, .m32 = &A64.cortex_a76 },
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E{ .part = 0x805, .m64 = &A64.cortex_a76, .m32 = &A64.cortex_a76 },
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E{ .part = 0xc00, .m64 = &A64.falkor },
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E{ .part = 0xc01, .m64 = &A64.saphira },
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};
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fn isKnown(core: CoreInfo, is_64bit: bool) ?*const Target.Cpu.Model {
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const models = switch (core.implementer) {
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0x41 => &ARM,
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0x42 => &Broadcom,
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0x43 => &Cavium,
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0x46 => &Fujitsu,
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0x48 => &HiSilicon,
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0x51 => &Qualcomm,
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else => return null,
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};
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inline for (models) |model| {
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if (model[0] == part)
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return if (is_64bit) model[2] else model[1];
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for (models) |model| {
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if (model.part == core.part and
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(model.variant == null or model.variant.? == core.variant))
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return if (is_64bit) model.m64 else model.m32;
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}
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return null;
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@@ -287,8 +339,7 @@ const ArmCpuinfoImpl = struct {
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var known_models: [self.cores.len]?*const Target.Cpu.Model = undefined;
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for (self.cores[0..self.core_no]) |core, i| {
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known_models[i] =
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cpu_models.isKnown(core.implementer, core.part, is_64bit);
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known_models[i] = cpu_models.isKnown(core, is_64bit);
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}
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// XXX We pick the first core on big.LITTLE systems, hopefully the
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