zig

commit e98e58691f2c0759c8534080446cf6faecd30eb0 (tree)
parent 019c8844811ffb8b385ac8891cfd17cbf60d104a
Author: Jacob Young <jacobly0@users.noreply.github.com>
Date:   Mon,  8 May 2023 18:34:45 -0400

x86_64: fix crash with logging enabled

Diffstat:
M
src/arch/x86_64/CodeGen.zig
 | 
19
++++++++++---------

1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/src/arch/x86_64/CodeGen.zig b/src/arch/x86_64/CodeGen.zig
@@ -1460,6 +1460,15 @@ fn asmMemoryRegister(self: *Self, tag: Mir.Inst.FixedTag, m: Memory, reg: Regist
 }
 
 fn asmMemoryImmediate(self: *Self, tag: Mir.Inst.FixedTag, m: Memory, imm: Immediate) !void {
+    const payload = try self.addExtra(Mir.Imm32{ .imm = switch (imm) {
+        .signed => |s| @bitCast(u32, s),
+        .unsigned => |u| @intCast(u32, u),
+    } });
+    assert(payload + 1 == switch (m) {
+        .sib => try self.addExtra(Mir.MemorySib.encode(m)),
+        .rip => try self.addExtra(Mir.MemoryRip.encode(m)),
+        else => unreachable,
+    });
     _ = try self.addInst(.{
         .tag = tag[1],
         .ops = switch (m) {
@@ -1475,17 +1484,9 @@ fn asmMemoryImmediate(self: *Self, tag: Mir.Inst.FixedTag, m: Memory, imm: Immed
         },
         .data = .{ .x = .{
             .fixes = tag[0],
-            .payload = try self.addExtra(Mir.Imm32{ .imm = switch (imm) {
-                .signed => |s| @bitCast(u32, s),
-                .unsigned => |u| @intCast(u32, u),
-            } }),
+            .payload = payload,
         } },
     });
-    _ = switch (m) {
-        .sib => try self.addExtra(Mir.MemorySib.encode(m)),
-        .rip => try self.addExtra(Mir.MemoryRip.encode(m)),
-        else => unreachable,
-    };
 }
 
 fn asmMemoryRegisterRegister(