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x64: load float from memory to register on PIE targets

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This commit is contained in:
Jakub Konka
2022-05-19 20:24:06 +02:00
parent 5cbfd5819e
commit f766b25f82
1 changed files with 42 additions and 10 deletions
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52
src/arch/x86_64/CodeGen.zig
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@@ -6085,16 +6085,48 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
.direct_load,
.got_load,
=> {
try self.loadMemPtrIntoRegister(reg, Type.usize, mcv);
_ = try self.addInst(.{
.tag = .mov,
.ops = Mir.Inst.Ops.encode(.{
.reg1 = registerAlias(reg, abi_size),
.reg2 = reg.to64(),
.flags = 0b01,
}),
.data = .{ .imm = 0 },
});
switch (ty.zigTypeTag()) {
.Float => {
const base_reg = try self.register_manager.allocReg(null, .{ .selector_mask = gp });
try self.loadMemPtrIntoRegister(base_reg, Type.usize, mcv);
if (self.intrinsicsAllowed(ty)) {
const tag: Mir.Inst.Tag = switch (ty.tag()) {
.f32 => .mov_f32_avx,
.f64 => .mov_f64_avx,
else => return self.fail("TODO genSetReg from memory for {}", .{ty.fmtDebug()}),
};
_ = try self.addInst(.{
.tag = tag,
.ops = Mir.Inst.Ops.encode(.{
.reg1 = reg.to128(),
.reg2 = switch (ty.tag()) {
.f32 => base_reg.to32(),
.f64 => base_reg.to64(),
else => unreachable,
},
}),
.data = .{ .imm = 0 },
});
return;
}
return self.fail("TODO genSetReg from memory for float with no intrinsics", .{});
},
else => {
try self.loadMemPtrIntoRegister(reg, Type.usize, mcv);
_ = try self.addInst(.{
.tag = .mov,
.ops = Mir.Inst.Ops.encode(.{
.reg1 = registerAlias(reg, abi_size),
.reg2 = reg.to64(),
.flags = 0b01,
}),
.data = .{ .imm = 0 },
});
},
}
},
.memory => |x| switch (ty.zigTypeTag()) {
.Float => {