zig

commit feba8a83a7c4eda738ebcf619c33ade8d0dfbfa7 (tree)
parent 9a6fad2706d05743a512c9ab5b54ba91cf5956fa
Author: Alex Rønne Petersen <alex@alexrp.com>
Date:   Tue,  7 Oct 2025 00:45:27 +0200

std.debug.Dwarf: use 65 as the (fake) RISC-V PC register

32-63 conflict with the floating point registers. 64 is the Alternate Frame
Return Column.

Diffstat:
M
lib/std/debug/Dwarf.zig
 | 
2
+-
M
lib/std/debug/cpu_context.zig
 | 
2
+-

2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/lib/std/debug/Dwarf.zig b/lib/std/debug/Dwarf.zig
@@ -1435,7 +1435,7 @@ pub fn ipRegNum(arch: std.Target.Cpu.Arch) ?u16 {
         .loongarch32, .loongarch64 => 64,
         .mips, .mipsel, .mips64, .mips64el => 37,
         .powerpc, .powerpcle, .powerpc64, .powerpc64le => 357,
-        .riscv32, .riscv32be, .riscv64, .riscv64be => 32,
+        .riscv32, .riscv32be, .riscv64, .riscv64be => 65,
         .s390x => 65,
         .x86 => 8,
         .x86_64 => 16,
diff --git a/lib/std/debug/cpu_context.zig b/lib/std/debug/cpu_context.zig
@@ -1018,7 +1018,7 @@ pub const Riscv = extern struct {
     pub fn dwarfRegisterBytes(ctx: *Riscv, register_num: u16) DwarfRegisterError![]u8 {
         switch (register_num) {
             0...31 => return @ptrCast(&ctx.r[register_num]),
-            32 => return @ptrCast(&ctx.pc),
+            65 => return @ptrCast(&ctx.pc),
 
             else => return error.InvalidRegister,
         }