Commit Graph

231 Commits

Author SHA1 Message Date
Jacob Young
525f341f33 Zcu: introduce PerThread and pass to all the functions 2024-07-07 22:59:52 -04:00
Andrew Kelley
30ec43a6c7 Zcu: extract permanent state from File
Primarily, this commit removes 2 fields from File, relying on the data
being stored in the `files` field, with the key as the path digest, and
the value as the struct decl corresponding to the File. This table is
serialized into the compiler state that survives between incremental
updates.

Meanwhile, the File struct remains ephemeral data that can be
reconstructed the first time it is needed by the compiler process, as
well as operated on by independent worker threads.

A key outcome of this commit is that there is now a stable index that
can be used to refer to a File. This will be needed when serializing
error messages to survive incremental compilation updates.
2024-07-04 17:51:35 -07:00
mlugg
2f0f1efa6f compiler: type.zig -> Type.zig 2024-07-04 21:01:42 +01:00
mlugg
ded5c759f8 Zcu: store LazySrcLoc in error messages
This change modifies `Zcu.ErrorMsg` to store a `Zcu.LazySrcLoc` rather
than a `Zcu.SrcLoc`. Everything else is dominoes.

The reason for this change is incremental compilation. If a failed
`AnalUnit` is up-to-date on an update, we want to re-use the old error
messages. However, the file containing the error location may have been
modified, and `SrcLoc` cannot survive such a modification. `LazySrcLoc`
is designed to be correct across incremental updates. Therefore, we
defer source location resolution until `Compilation` gathers the compile
errors into the `ErrorBundle`.
2024-07-04 21:01:41 +01:00
David Rubin
e73ae94b36 riscv: remove deprecated Module usages 2024-06-23 15:26:14 +01:00
Andrew Kelley
0fcd59eada rename src/Module.zig to src/Zcu.zig
This patch is a pure rename plus only changing the file path in
`@import` sites, so it is expected to not create version control
conflicts, even when rebasing.
2024-06-22 22:59:56 -04:00
David Rubin
4fd8900337 riscv: rewrite "binOp"
Reorganize how the binOp and genBinOp functions work.

I've spent quite a while here reading exactly through the spec and so many
tests are enabled because of several critical issues the old design had.

There are some regressions that will take a long time to figure out individually
so I will ignore them for now, and pray they get fixed by themselves. When
we're closer to 100% passing is when I will start diving into them one-by-one.
2024-06-13 02:24:39 -07:00
David Rubin
a9ef016943 riscv: implement airArrayToSlice 2024-06-13 02:22:34 -07:00
David Rubin
a270c6f8c8 riscv: implement optional logic 2024-06-13 02:22:33 -07:00
David Rubin
d69c48370a riscv: integer + float @abs 2024-06-13 02:22:06 -07:00
David Rubin
206e66858c riscv: rename Self to Func
Very similar reasoning to the Wasm backend. I believe that "Self" is
not the most descriptive possible name here and "Func" better explains it.

The generation is happening for a Function, and accessing "Func" is like accessing
the context of that current function.
2024-06-13 02:22:05 -07:00
David Rubin
c10d1c6a75 riscv: implement more arithmetic instructions 2024-06-13 02:22:05 -07:00
David Rubin
083b7b483e riscv: zero registers when using register-wide operations
what was happening is that instructions like `lb` were only affecting the lower bytes of the register and leaving the top dirty. this would lead to situtations were `cmp_eq` for example was using `xor`, which was failing because of the left-over stuff in the top of the register.

with this commit, we now zero out or truncate depending on the context, to ensure instructions like xor will provide proper results.
2024-06-13 02:22:04 -07:00
David Rubin
b67995689d riscv: add airAggregateInit for arrays 2024-06-13 02:22:04 -07:00
David Rubin
b2cb090c37 riscv: float args 2024-06-13 02:21:39 -07:00
David Rubin
031d8248e0 riscv: first sign of floats! 2024-06-13 02:21:38 -07:00
David Rubin
7ed2f2156f riscv: fix register clobber in certain edge cases 2024-06-13 02:21:38 -07:00
David Rubin
05de6c279b riscv: std.fmt.format running
- implements `airSlice`, `airBitAnd`, `airBitOr`, `airShr`.

- got a basic design going for the `airErrorName` but for some reason it simply returns
empty bytes. will investigate further.

- only generating `.got.zig` entries when not compiling an object or shared library

- reduced the total amount of ops a mnemonic can have to 3, simplifying the logic
2024-06-13 02:20:47 -07:00
David Rubin
55b28c7e44 riscv: PRO member function calls
this is enough progress for us to be able to call `stdout.write`!
2024-06-13 02:19:40 -07:00
David Rubin
c457f35da5 riscv: arbitrary sized arrays 2024-06-13 02:19:40 -07:00
David Rubin
f34dcd067b riscv: basic libc varargs 2024-06-13 02:19:39 -07:00
David Rubin
fcafaae747 riscv: get basic libc interop 2024-06-13 02:19:39 -07:00
David Rubin
004d0c8978 riscv: switch progress + by-ref return progress 2024-06-13 02:19:38 -07:00
Andrew Kelley
9be8a9000f Revert "implement @expect builtin (#19658)"
This reverts commit a7de02e052.

This did not implement the accepted proposal, and I did not sign off
on the changes. I would like a chance to review this, please.
2024-05-22 09:57:43 -07:00
David Rubin
a7de02e052 implement @expect builtin (#19658)
* implement `@expect`

* add docs

* add a second arg for expected bool

* fix typo

* move `expect` to use BinOp

* update to newer langref format
2024-05-22 10:51:16 -05:00
David Rubin
1dfdc21c31 riscv: intcast got_addr
the recent merge strings PR made `got_addr` `i64` and now requires an `@intCast`.
2024-05-11 02:17:24 -07:00
David Rubin
ffb63a05a3 riscv: finally fix bug + airAggregateInit
i just hadn't realized that I placed the `riscv_start` branch in the non-simplified
starts
2024-05-11 02:17:24 -07:00
David Rubin
2fd83d8c0a riscv: by-value structs + @min 2024-05-11 02:17:24 -07:00
David Rubin
a30af172e8 riscv: math progress 2024-05-11 02:17:24 -07:00
David Rubin
a615fbc1f8 riscv: mutable globals 2024-05-11 02:17:24 -07:00
David Rubin
d9e0cafe64 riscv: add stage2_riscv to test matrix and bypass failing tests 2024-05-11 02:17:24 -07:00
David Rubin
e622485df8 riscv: actually working test runner 2024-05-11 02:17:11 -07:00
David Rubin
d19b77d63f riscv: back to hello world panics 2024-05-11 02:17:11 -07:00
David Rubin
cc204e2365 riscv: spill args immediately to prevent clobbers 2024-05-11 02:17:11 -07:00
David Rubin
6740c1f084 riscv: big rewrite to use latest liveness
this one is even harder to document then the last large overhaul.

TLDR;
- split apart Emit.zig into an Emit.zig and a Lower.zig
- created seperate files for the encoding, and now adding a new instruction
is as simple as just adding it to a couple of switch statements and providing the encoding.
- relocs are handled in a more sane maner, and we have a clear defining boundary between
lea_symbol and load_symbol now.
- a lot of different abstractions for things like the stack, memory, registers, and others.
- we're using x86_64's FrameIndex now, which simplifies a lot of the tougher design process.
- a lot more that I don't have the energy to document. at this point, just read the commit itself :p
2024-05-11 02:17:11 -07:00
David Rubin
9d0bb6371d riscv: almost @errorName but not loading correctly 2024-05-11 02:17:11 -07:00
David Rubin
8ac239ebce riscv: add enough components to get a test runner working 2024-05-11 02:17:11 -07:00
David Rubin
c0629c3539 riscv: implement airNot 2024-05-11 02:17:11 -07:00
David Rubin
4ce85f930e riscv: implement structFieldPtr and retLoad 2024-05-11 02:17:11 -07:00
David Rubin
ece70e08a0 riscv: pass optionals by register_pair for resolveCallingConventionValues 2024-05-11 02:17:11 -07:00
David Rubin
26ce82d98e riscv: correctly derefence load_symbol in genSetReg 2024-05-11 02:17:11 -07:00
David Rubin
3bf008a3d0 riscv: implement slices 2024-05-11 02:17:11 -07:00
David Rubin
350ad90cee riscv: totally rewrite how we do loads and stores
this commit is a little too large to document fully, however the main gist of it this

- finish the `genInlineMemcpy` implement
- rename `setValue` to `genCopy` as I agree with jacob that it's a better name
- add in `genVarDbgInfo` for a better gdb experience
- follow the x86_64's method for genCall, as the procedure is very similar for us
- add `airSliceLen` as it's trivial
- change up the `airAddWithOverflow implementation a bit
- make sure to not spill of the elem_ty is 0 size
- correctly follow the RISC-V calling convention and spill the used calle saved registers in the prologue
and restore them in the epilogue
- add `address`, `deref`, and `offset` helper functions for MCValue. I must say I love these,
they make the code very readable and super verbose :)
- fix a `register_manager.zig` issue where when using the last register in the set, the value would overflow at comptime.
was happening because we were adding to `max_id` before subtracting from it.
2024-05-11 02:17:11 -07:00
David Rubin
3c0015c828 riscv: implement a basic @intCast
the truncation panic logic is generated in Sema, so I don't need to roll anything
of my own. I add all of the boilerplate for that detecting the truncation and it works
in basic test cases!
2024-05-11 02:17:11 -07:00
David Rubin
b28c966e33 riscv: fix overflow checks in addition. 2024-05-11 02:17:11 -07:00
David Rubin
c96989aa4b riscv: correctly index struct field access
when the struct is in stack memory, we access it using a byte-offset,
because that's how the stack works. on the other hand when the struct
is in a register, we are working with bits and the field offset should
be a bit offset.
2024-05-11 02:17:11 -07:00
David Rubin
09b7aabe09 riscv: add allocReg helper, and clean up some comparing logic
- Added the basic framework for panicing with an overflow in `airAddWithOverflow`, but there is no check done yet.
- added the `cmp_lt`, `cmp_gte`, and `cmp_imm_eq` MIR instructions, and their respective functionality.
2024-05-11 02:17:11 -07:00
David Rubin
08452b1add riscv: correct the order of the return epilogue 2024-05-11 02:17:11 -07:00
David Rubin
f1fe5c937e riscv: pointer work
lots of thinking later, ive begun to grasp my head around how the pointers should work. this commit allows basic pointer loading and storing to happen.
2024-05-11 02:17:11 -07:00
David Rubin
9229321400 riscv: change up how we do args
- before we were storing each arg in it's own function arg register. with this commit now we store the args in the fa register before calling as per the RISC-V calling convention, however as soon as we enter the callee, aka in airArg, we spill the argument to the stack. this allows us to spend less effort worrying about whether we're going to clobber the function arguments when another function is called inside of the callee.

- we were actually clobbering the fa regs inside of resolveCallingConvetion, because of the null argument to allocReg. now each lock is stored in an array which is then iterated over and unlocked, which actually aids in the first point of this commit.
2024-05-11 02:17:11 -07:00