Commit Graph

26 Commits

Author SHA1 Message Date
Andrew Kelley
a2abbeef90 stage2: rework a lot of stuff
AstGen:
 * rename the known_has_bits flag to known_non_opv to make it better
   reflect what it actually means.
 * add a known_comptime_only flag.
 * make the flags take advantage of identifiers of primitives and the
   fact that zig has no shadowing.
 * correct the known_non_opv flag for function bodies.

Sema:
 * Rename `hasCodeGenBits` to `hasRuntimeBits` to better reflect what it
   does.
   - This function got a bit more complicated in this commit because of
     the duality of function bodies: on one hand they have runtime bits,
     but on the other hand they require being comptime known.
 * WipAnonDecl now takes a LazySrcDecl parameter and performs the type
   resolutions that it needs during finish().
 * Implement comptime `@ptrToInt`.

Codegen:
 * Improved handling of lowering decl_ref; make it work for
   comptime-known ptr-to-int values.
   - This same change had to be made many different times; perhaps we
     should look into merging the implementations of `genTypedValue`
     across x86, arm, aarch64, and riscv.
2022-01-24 21:53:57 -07:00
joachimschmidt557
c710d5eefe stage2 ARM: implement wrap_errunion_err for empty payloads 2022-01-02 15:15:59 -05:00
joachimschmidt557
845531dde1 stage2 ARM: implement airUnwrapErrErr + airCmp for error sets 2022-01-01 11:16:38 +01:00
joachimschmidt557
f8163f7eaf stage2 ARM: implement airCall for function pointers 2022-01-01 11:16:34 +01:00
joachimschmidt557
69d03d3a29 stage2 ARM: implement struct_field_ptr and struct_field_val 2021-12-30 14:39:06 +01:00
joachimschmidt557
c0ae9647f9 stage2 ARM: implement slice_elem_val for types with size <= 4 2021-12-28 20:38:37 -05:00
joachimschmidt557
c55f58d8bb stage2 ARM: implement is_err and is_non_err for simple error unions 2021-12-21 23:13:30 +01:00
joachimschmidt557
edcebe7013 stage2 ARM: implement is_null and is_non_null for ptr-like optionals 2021-12-21 23:13:30 +01:00
joachimschmidt557
9892684d35 stage2 ARM: spill insts currently in compare flags if necessary 2021-12-18 15:23:25 -08:00
joachimschmidt557
2f18c5955a stage2 ARM: Implement calling with stack parameters 2021-12-04 18:16:23 -08:00
joachimschmidt557
5806c386eb stage2 codegen: re-allocate result register in finishAir
In some cases (such as bitcast), an operand may be the same MCValue as
the result. If that operand died and was a register, it was freed by
processDeath. We have to "re-allocate" the register.
2021-08-20 19:06:30 -04:00
joachimschmidt557
224fe49be2 stage2 ARM: add test cases for bit shifts 2021-08-20 23:37:41 +02:00
joachimschmidt557
84039a57e4 stage2 codegen: Implement genTypedValue for enums 2021-07-30 17:53:33 -04:00
Andrew Kelley
615d45da77 Merge remote-tracking branch 'origin/master' into stage2-whole-file-astgen
Conflicts:
 * src/codegen/spirv.zig
 * src/link/SpirV.zig

We're going to want to improve the stage2 test harness to print
the source file name when a compile error occurs otherwise std lib
contributors are going to see some confusing CI failures when they cause
stage2 AstGen compile errors.
2021-05-17 19:30:38 -07:00
Andrew Kelley
8a7a07f30d stage2: test cases take advantage of pub fn main support 2021-05-17 16:09:20 -07:00
joachimschmidt557
65cee0b3fd stage2 ARM: correct spilling in genArmMul as well 2021-05-17 17:18:01 -04:00
Andrew Kelley
b109daacdd stage2: fix test cases to add pub on exported _start fn
This way the start code respects them.
2021-05-12 23:17:24 -07:00
joachimschmidt557
f2a3368891 stage2 ARM: Add spill registers test 2021-05-09 08:48:58 +02:00
joachimschmidt557
4fe575f47b stage2 ARM: Add fibonacci test 2021-04-11 10:19:36 +02:00
joachimschmidt557
1b657e6e41 stage2 codegen: Make sure function return value is in a callee
preserved register
2021-03-31 23:27:50 +02:00
joachimschmidt557
278bd60732 stage2 ARM: Add tests for basic integer multiplication 2021-03-02 00:34:41 +01:00
Andrew Kelley
30a824cb9e astgen: eliminate rlWrapPtr and all its callsites
The following AST avoids unnecessary derefs now:
 * error set decl
 * field access
 * array access
 * for loops: replace ensure_indexable and deref on the len_ptr with a
   special purpose ZIR instruction called indexable_ptr_len.

Added an error note when for loop operand is the wrong type.

I also accidentally implemented `@field`.
2021-01-19 00:38:53 -07:00
joachimschmidt557
a2ab2fb9b0 stage2 ARM: Add simple tests for conditional branching 2021-01-01 12:22:17 +01:00
joachimschmidt557
45a88be573 stage2 ARM: add test cases for binary bitwise operations 2020-12-21 19:24:23 +01:00
joachimschmidt557
ceebcb2b4d stage2 ARM: add test case for addition 2020-11-28 23:26:17 +01:00
joachimschmidt557
fb58fb2d8d stage2 ARM: add testcases for non-leaf fns, parameters, return values 2020-10-03 12:52:04 +02:00