Koakuma
c5b99267c0
stage2: sparc64: Remove saved_regs_stack_space calculation
...
SPARC does not have an explicit notion of saving/restoring registers.
The usual windowing mechanism (save/restore/return) already takes care of that
for us.
2022-05-26 13:48:39 +07:00
Koakuma
3923722cc6
stage2: sparc64: Account for stack bias & reserved area in genSetReg
...
genSetReg with ptr_stack_offset should add the bias and reserved area
before emitting the instruction.
2022-05-26 13:48:29 +07:00
Koakuma
5fa971610e
stage2: sparc64: Change binOpImmediate immediates to u12
...
Sync with the check in binOp.
2022-05-26 13:09:56 +07:00
Koakuma
0310d88d7e
stage2: sparc64: Add cmp and mov synthetic instructions
2022-05-26 13:08:39 +07:00
Jakub Konka
e95dfac03e
regalloc: make register class bitmask non-optional
2022-05-19 23:54:48 +02:00
Jakub Konka
549174f743
regalloc: allow for optional selector mask when allocating
2022-05-19 19:39:32 +02:00
Andrew Kelley
b6798c26ef
stage2: fix pointer arithmetic result type
...
This makes it so the result of doing pointer arithmetic creates a new
pointer type that has adjusted alignment.
2022-05-17 23:50:38 -07:00
Andrew Kelley
df74c45fa7
Merge pull request #11501 from Vexu/stage2-err-return-trace
...
stage2: error return traces
2022-05-17 03:27:03 -04:00
Veikka Tuominen
eee8fffec7
stage2: implement error return traces
2022-05-16 17:42:51 -07:00
Koakuma
7245aad689
stage2: sparc64: Implement airBinOp for addition
2022-05-16 23:30:54 +07:00
Koakuma
67a1fedf84
stage2: sparc64: Implement airUnwrapErrErr
2022-05-16 23:30:54 +07:00
Koakuma
77eef33c04
stage2: sparc64: Implement airStructFieldPtrIndex
2022-05-16 23:30:54 +07:00
Koakuma
26116211ec
stage2: sparc64: Implement inline memcpy for genSetStack
2022-05-16 23:30:54 +07:00
Koakuma
7822426ff2
stage2: sparc64: Implement airSliceElemVal
2022-05-16 23:30:54 +07:00
Koakuma
ccf438e4de
stage2: sparc64: Replace freezeRegs with RegisterLock
2022-05-16 23:30:54 +07:00
Koakuma
26e3d36d74
stage2: sparc64: Implement airSliceLen
2022-05-16 23:30:54 +07:00
Koakuma
8ea80fdf7a
stage2: sparc64: Implement airLoop
2022-05-16 23:30:47 +07:00
Koakuma
e4a725c597
stage2: sparc64: Implement airBitCast
2022-05-16 23:17:11 +07:00
Koakuma
0c8ce9ed9d
stage2: sparc64: Implement airCmp
2022-05-16 23:17:11 +07:00
Koakuma
ae2d6b7eea
stage2: sparc64: Add BPr support for airCondBr
2022-05-16 23:17:11 +07:00
Koakuma
8f8853cd4f
stage2: sparc64: Implement airLoad/airStore
2022-05-16 23:17:06 +07:00
Koakuma
0b54649cac
stage2: sparc64: Implement error value generation
2022-05-16 22:48:49 +07:00
Koakuma
3ab6634370
stage2: sparc64: Implement airAlloc
2022-05-16 22:48:49 +07:00
Koakuma
2770f9a034
stage2: sparc64: Implement airBr
2022-05-16 22:47:53 +07:00
Koakuma
b6de8d2565
stage2: sparc64: Implement airUnwrapErrPayload
2022-05-16 22:47:53 +07:00
Koakuma
2dc2ab091e
stage2: sparc64: Implement airCondBr from flags register
2022-05-16 22:47:53 +07:00
Koakuma
fd781195de
stage2: sparc64: Split the conditionals between integer and FP ones
...
On SPARCv9 the integer and FP conditional branch codes doesn't align
with each other at all, so the two need to be treated separately.
2022-05-16 22:47:52 +07:00
Koakuma
662a61fcc3
stage2: sparc64: Implement airIsErr and airIsNonErr
2022-05-16 22:47:52 +07:00
Koakuma
fb0692334e
target: Rename sparcv9 -> sparc64
...
Rename all references of sparcv9 to sparc64, to make Zig align more with
other projects. Also, added new function to convert glibc arch name to Zig
arch name, since it refers to the architecture as sparcv9.
This is based on the suggestion by @kubkon in PR 11847.
(https://github.com/ziglang/zig/pull/11487#pullrequestreview-963761757 )
2022-05-13 16:43:59 -04:00
