zig0

commit 4e7a84106a97d27116cf56757123763b32fda889 (tree)
parent b6da8dd6cd34a408c8b2568ca4c4a79acc0a3bcc
Author: Motiejus Jakštys <motiejus@jakstys.lt>
Date:   Fri, 13 Feb 2026 20:11:22 +0000

astgen: fix cppcheck warnings (variableScope, uninitvar)

Inline index_inst at usage site to narrow scope, initialize
var_init_rl.ctx to RI_CTX_NONE (matching upstream default).

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>

Diffstat:
M
astgen.c
 | 
4
++--

1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/astgen.c b/astgen.c
@@ -5350,7 +5350,6 @@ static uint32_t forExpr(
     // then_scope. However, the load must be removed from instructions in the
     // meantime or it appears to be part of parent_gz.
     uint32_t index = addUnNode(&loop_scope, ZIR_INST_LOAD, index_ptr, node);
-    uint32_t index_inst = index - ZIR_REF_START_INDEX;
     ag->scratch_inst_len--; // pop from loop_scope (AstGen.zig:6956)
 
     // Condition: added to cond_scope (AstGen.zig:6958-6962).
@@ -5467,7 +5466,7 @@ static uint32_t forExpr(
     {
         // Reset loop_scope instructions and re-add index + cond_block.
         loop_scope.instructions_top = ag->scratch_inst_len;
-        gzAppendInstruction(&loop_scope, index_inst);
+        gzAppendInstruction(&loop_scope, index - ZIR_REF_START_INDEX);
         gzAppendInstruction(&loop_scope, cond_block);
 
         // Increment the index variable (AstGen.zig:7100-7108).
@@ -6533,6 +6532,7 @@ static void varDecl(GenZir* gz, Scope* scope, uint32_t node,
             var_init_rl.data = alloc_ref;
             var_init_rl.src_node = 0;
         }
+        var_init_rl.ctx = RI_CTX_NONE;
         uint32_t init_ref = exprRl(gz, scope, var_init_rl, init_node);
         (void)init_ref;