zig

commit bc282a6389fce178acba6462cdadd52a1aa1026a (tree)
parent 81ef502f08e966fb57c4313a9c7e9b6f9f55aa4a
Author: Alex Rønne Petersen <alex@alexrp.com>
Date:   Mon,  9 Feb 2026 23:34:48 +0100

generate_linux_syscalls: add loongarch32

Diffstat:
M
tools/generate_linux_syscalls.zig
 | 
1
+

1 file changed, 1 insertion(+), 0 deletions(-)
diff --git a/tools/generate_linux_syscalls.zig b/tools/generate_linux_syscalls.zig
@@ -159,6 +159,7 @@ const architectures: []const Arch = &.{
     .{ .@"var" = "Arm64", .table = .generic, .abi = &.{ .common, .@"64", .renameat, .rlimit, .memfd_secret } },
     .{ .@"var" = "RiscV32", .table = .generic, .abi = &.{ .common, .@"32", .riscv, .memfd_secret } },
     .{ .@"var" = "RiscV64", .table = .generic, .abi = &.{ .common, .@"64", .riscv, .rlimit, .memfd_secret } },
+    .{ .@"var" = "LoongArch32", .table = .generic, .abi = &.{ .common, .@"32" } },
     .{ .@"var" = "LoongArch64", .table = .generic, .abi = &.{ .common, .@"64" } },
     .{ .@"var" = "Arc", .table = .generic, .abi = &.{ .common, .@"32", .arc, .time32, .renameat, .stat64, .rlimit } },
     .{ .@"var" = "CSky", .table = .generic, .abi = &.{ .common, .@"32", .csky, .time32, .stat64, .rlimit } },